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Verilog Designer's Library

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Verilog Designer's Library

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Description

  • Copyright 1999
  • Dimensions: 7 X 9-1/4
  • Pages: 432
  • Edition: 1st
  • Book
  • ISBN-10: 0-13-081154-8
  • ISBN-13: 978-0-13-081154-7
  • eBook (Adobe DRM)
  • ISBN-10: 0-13-244140-3
  • ISBN-13: 978-0-13-244140-7

Ready-to-use building blocks for integrated circuit design.

Why start coding from scratch when you can work from this library of pre-tested routines, created by an HDL expert? There are plenty of introductory texts to describe the basics of Verilog, but Verilog Designer's Library is the only book that offers real, reusable routines that you can put to work right away.

Verilog Designer's Library organizes Verilog routines according to functionality, making it easy to locate the material you need. Each function is described by a behavioral model to use for simulation, followed by the RTL code you'll use to synthesize the gate-level implementation. Extensive test code is included for each function, to assist you with your own verification efforts.

Coverage includes:

  • Essential Verilog coding techniques
  • Basic building blocks of successful routines
  • State machines and memories
  • Practical debugging guidelines

Although Verilog Designer's Library assumes a basic familiarity with Verilog structure and syntax, it does not require a background in programming. Beginners can work through the book in sequence to develop their skills, while experienced Verilog users can go directly to the routines they need. Hardware designers, systems analysts, VARs, OEMs, software developers, and system integrators will find it an ideal sourcebook on all aspects of Verilog development.

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Table of Contents

I. CODING TECHNIQUES.

1. General Coding Techniques.

Code Structure. Comments. Do Not Use Disable Instructions.

2. Behavioral Coding Techniques.

Eliminate Periodic Instructions. Eliminate Event Order Dependencies.

3. RTL Coding Techniques.

Synchronous Design. Allowable Uses of Asynchronous Logic.

4. Synthesis Issues.

Correlated Unknown Signals. State Machines. Optimizing Out Terms. Always Blocks.

5. Simulation Issues.

Simulate The Corner Cases. Use Code Coverage Tools. Use The Triple Equals. Use The $display And $stop Statements.

II. BASIC BUILDING BLOCKS.

6. The J-K Flip Flop.

Behavioral Code. RTL Code. Simulation Code.

7. The Shift Register.

Behavioral Code. RTL Code. Simulation Code.

8. The Counter.

Behavioral Code. RTL Code. Simulation Code.

9. The Adder.

Behavioral Code. RTL Code. Simulation Code.

III. STATE MACHINES.

10. The Moore State Machine.

Behavioral Code. RTL Code. Simulation Code.

11. The Mealy State Machine.

Behavioral Code. RTL Code. Simulation Code.

12. The One-Hot State Machine for FPGAs.

RTL Code. Simulation Code.

IV. MISCELLANEOUS COMPLEX FUNCTIONS.

13. The Linear Feedback Shift Register (LFSR).

Behavioral Code. RTL Code. Simulation Code.

14. The Encrypter/Decrypter.

Behavioral Code. RTL Code. Simulation Code.

15. The Phase Locked Loop (PLL).

Behavioral Code. RTL Code. Simulation Code.

16. The Unsigned Integer Multiplier.

Behavioral Code. RTL Code. Simulation Code.

17. The Signed Integer Multiplier.

Behavioral Code. RTL Code. Simulation Code.

V. ERROR DETECTION AND CORRECTION.

18. The Parity Generator and Checker.

Implementation Code. Simulation Code.

19. Hamming Code Logic.

Implementation Code. Simulation Code.

20. The Checksum.

Implementation Code. Simulation Code.

21. The Cyclic Redundancy Check (CRC).

Behavioral Code. RTL Code. Simulation Code.

VI. MEMORIES.

22. The Random Access Memory (RAM).

Implementation Code. Simulation Code.

23. The Dual Port RAM.

Implementation Code. Simulation Code.

24. The Synchronous FIFO.

Behavioral Code. RTL Code. Simulation Code.

25. The Synchronizing FIFO.

Behavioral Code. RTL Code. Simulation Code.

VII. MEMORY CONTROLLERS.

26. The SRAM/ROM Controller.

Behavioral Code. RTL Code. Simulation Code.

27. The Synchronous SRAM Controller.

Behavioral Code. RTL Code. Simulation Code.

28. The DRAM Controller.

Behavioral Code. RTL Code. Simulation Code.

29. The Fast Page Mode DRAM Controller.

Behavioral Code. RTL Code. Simulation Code.

Appendix A: Resources.

Glossary.

Index.

Preface

Preface

Hardware Description Languages (HDLs) are fast becoming the design method of choice for electrical engineers. Their ability to model and simulate all levels of design, from abstract algorithms and behavioral functions to register transfer level (RTL) and gate level descriptions, make them extremely powerful tools. Synthesis software allows engineers to take these very high-level descriptions of chips and systems and automatically convert them to real netlists for manufacturing, at least in theory. As chip complexity increases, and gate counts commonly reach 100,000 and above, HDLs become the only practical design method. Even FPGA densities have increased to the point where HDLs are the most efficient design entry method. The benefits of HDLs are even trickling into the areas of PCB design, where it is useful to have one set of tools for simulating integrated circuits and PCBs and the systems into which they are incorporated. The value of using HDLs to model a system on a behavioral level also cannot be ignored as system architects use them to determine and eliminate bottlenecks and improve overall performance of a wide variety of systems.

WHAT IS THIS BOOK ABOUT?

Of the HDLs available, Verilog is one of the most popular. Many designs have been created in Verilog and a large number of Verilog simulators, compilers, synthesizers, and other tools are available from numerous vendors. Its powerful features have led to many applications in all areas of chip design.

This book provides a library of general purpose routines that simplify the task of Verilog programming and enhance existing designs. I have taken input from other designer engineers to make sure that this library covers many of the common functions that a hardware designer is likely to need. Beginning Verilog designers can use these routines as tutorials in order to learn the language or to increase their understanding of it. Experienced Verilog designers can use these routines as a reference and a starting point for real world designs. Rather than redevelop code for common functions, you can simply cut and paste these routines and modify them for your own particular needs. Each routine includes a brief but complete description plus fully documented Verilog code for Behavioral and Register Transfer Level (RTL) implementations. In addition, the Verilog simulation code that was used to verify each hardware module is also included. This code is also available on the enclosed diskette. Feel free to include the Verilog code, royalty-free, in your own designs.

HOW IS THIS BOOK ORGANIZED?

The routines are organized according to functionality. Each chapter addresses a common type of function such as state machines, memory models, or data flow. Each section of a chapter gives an example of code to implement that particular function. Also, successive sections, in general, have increasingly more complex examples. Each function is described using a behavioral model followed by an RTL model. Because behavioral models do not include low level implementation details, they simulate very fast and can be used for quickly evaluating a proposed architecture for a chip or a system. The behavioral models are also useful for creating a simulation environment for your design. The inputs to a chip can be stimulated using behavioral models that might represent something simple, like DRAMs connected to a microprocessor, or something complex like workstations connected to a network. The RTL code, on the other hand, is needed to create real hardware. It is written with synthesis in mind. Despite the sophistication of many synthesis tools, these programs need to make decisions about the gate level implementation based on the RTL code. For this reason, the RTL descriptions must be written in such a way so that there is no ambiguity with respect to what the designer has in mind. Also, the Verilog simulation code is given that is used to test the functionality of each module. This is important because good simulation code will determine whether the hardware will work correctly.

The organization of the book has another advantage. If you are a novice Verilog designer, you can start by studying the simple examples in the beginning and work your way up to the complex examples toward the end. This will give you a very comprehensive understanding of Verilog. If you are an experienced Verilog designer, you can simply jump right to the section that most closely matches your particular design needs. Take that function, play with it, and modify it to suit your design. This will save a significant amount of time by eliminating the need to write the code from scratch.

WHO IS THIS BOOK FOR?

This book is for Verilog users at any level. It assumes a basic familiarity with Verilog structure and syntax. It does not assume any programming background. The book is particularly well suited to hardware designers learning Verilog without having written programs previously, as well as those who have used languages such as BASIC, C, FORTRAN, or Pascal. The book will also appeal to experienced Verilog designers who can skip to the sections that fit their own needs.

This book is valuable to hardware designers, systems analysts, students, teachers, trainers, vendors, system integrators, VARs, OEMs, software developers. and consultants. It is an ideal follow-on or sourcebook for those who have just completed an introductory book or course on Verilog programming.

SUPPORT, SOURCE DISKS, AND COMMENTS

I have simulated all of the examples using SILOS III version 99.115 from Simucad Inc. All of the RTL code has been synthesized using FPGA Express version 3.4 from Synopsys, Inc. As with all published programs, there will surely be last minute changes, which appear on the README.TXT file on the accompanying diskette.

The publisher and I welcome your comments regarding the routines in the book. If you find bugs, discover better ways to accomplish tasks, or can suggest other routines that you think should be included, I am eager to hear about them. To receive notification of revisions and upgrades to the Library, please mail the registration form that appears later in this book.

Bob Zeidman
Cupertino, California

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