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Universal Serial Bus System Architecture, 2nd Edition

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Universal Serial Bus System Architecture, 2nd Edition


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  • Copyright 2001
  • Dimensions: 7-3/8" x 9-1/4"
  • Pages: 544
  • Edition: 2nd
  • Book
  • ISBN-10: 0-201-30975-0
  • ISBN-13: 978-0-201-30975-1

Universal Serial Bus System Architecture, Second Edition, based on the 2.0 version of the Universal Serial Bus specification, provides in-depth coverage and a detailed discussion of USB. It focuses on the USB protocol, signaling environment, and electrical specifications, along with the hardware/software interaction required to configure and access USB devices. Key topics include:

  • Hot plug support (detection of low-, full-, and high-speed devices)
  • Electrical signaling at the 1.5, 12, and 480Mb/s rates
  • 2.0 hub operation (including split transaction support)
  • 2.0 high-speed protocol (including high-bandwidth and ping transactions)
  • High-speed transceiver test modes
  • Suspend/resume operations
  • Device descriptors
  • Device requests (commands)
  • USB transaction protocols (low-, full-, and high-speed)
  • Bus-powered devices
  • Self-powered devices
  • Error detection and handling
  • Device configuration
  • Device classes

This second edition has been updated to reflect the changes in the USB specification from the original 1.0 to the current 2.0. The USB 2.0 specification defines high-speed transactions operating at 480Mb/s that increase throughput by a factor of 40 over the older USB devices. New high-bandwidth, ping, and split transactions have also been added to further increase efficiency of the high-speed protocol. The USB 2.0 specification makes major improvements to USB, while maintaining backward compatibility with 1.0 and 1.1 USB devices. If you design or test hardware or software that involves USB, you wouldn't want to miss the important updates in this book. Universal Serial Bus System Architecture, Second Edition, is an essential, time-saving tool.

The accompanying CD-ROM includes an 85-minute USB 2.0 overview video by Don Anderson, featuring an introduction to the basic concepts underlying USB 2.0 bus operation and protocol. Topics covered include terminology, design goals of USB, a review of low- and full-speed operation used by USB 1.0 and 1.1 systems and devices, an introduction to USB 2.0 high-speed transfers, and how USB 2.0 hubs use split transactions to provide backward compatibility to low- and full-speed devices.

The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title is designed to illustrate the relationship between the software and hardware and explains thoroughly the architecture, features, and operations of systems built using one particular type of chip or hardware specification.


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Table of Contents

About This Book.

The MindShare Architecture Series.

Cautionary Note.

Specifications This Book is Based On.

Organization of This Book.

Who Should Read this Book.

Prerequisite Knowledge.

Documentation Conventions.

Identification of Bit Fields (logical groups of bits or signals).

Visit Our Web Page.

We Want Your Feedback.


1. Design Goals of USB.

Shortcomings of the Original PC I/O Paradigm.

Limited System Resources.

End User Concerns.


The USB Paradigm.

Enhanced System Performance.

Hot Plug and Play Support.


Legacy Hardware/Software Support.

Low Cost.

Summary of Key USB Features.

How to Get the USB Specifications.

2. The Big Picture.


USB 1.x Systems and Devices.

Low-Speed and Full-Speed Devices.

How Transactions Are Generated.

Sharing the Bus.

Bandwidth Consideration Summary.

2.0 Systems and Devices.

Low-Speed and Full-Speed Devices in a 2.0 System.

High-Speed Devices in a 2.0 System.

High-Speed Bandwidth Summary.

The Players.

USB Client Drivers.

USB Bus Driver.

USB Host Controller Driver.

USB Host Controller/Root Hub.

USB Hubs.

USB Devices.

USB Communications Model.

Communications Flow.

Transfers, IRPs, Frames, and Packets.

Device Framework (how devices present themselves to software).

Device Descriptors.

Device Framework.

USB Peripheral Connection.

Full-Speed Hubs.

High-Speed Hubs.


3. Cables and Connectors.

The Connectors.

Series A Connectors.

Series B Connectors.


Low-Speed Cables.

Full- and High-Speed Cables.

Cable Power.

Electrical and Mechanical Specifications.

4. USB Cable Power Distribution.

USB Power.


Current Budget.

Over-Current Protection.

Voltage Drop Budget.

Power Switching.

Bus-Powered Hubs.

Power During Hub Configuration.

Bus-Powered Hub Attached to 500ma Port.

Bus-Powered Hub Attached to 100ma Port.

Bus-Powered Hub Attached to Port with >100ma but <500ma.

Current Limiting.

Bus-Powered Devices.

Low-Power Devices.

High-Power Devices.

Self-Powered Hubs.

Power During Configuration.

Current Limiting.

Self-Powered Devices.

Power During Configuration.


5. LS/FS Signaling Environment.


Detecting Device Attachment and Speed Detect.

Full-Speed Device Connect.

Low-Speed Device Connect.

Detecting Device Disconnect.

Bus Idle.

Device RESET.

Differential Signaling.

Differential Drivers.

Differential Receivers.

Start of Packet (SOP).

End of Packet (EOP).

Single-Ended Receivers.

NRZI Encoding.

Bit Stuffing.

Summary of USB Signaling States.

6. LS/FS Transfer Types & Scheduling.


Client Initiates Transfer.

Communications Pipes.

Communication Initiated by I/O Request Packets.

Frame-Based Transfers.

Transfer Types.

Isochronous Transfers.

Establishing Synchronous Connections.

The Feedback/Feed Forwarding Solution.

Interrupt Transfers.

Control Transfers.

Bulk Transfers.

7. Packets & Transactions.


Packets—The Basic Building Blocks of USB Transactions.

Synchronization Sequence.

Packet Identifier.

Packet-Specific Information.

Cyclic Redundancy Checking (CRC).

End of Packet (EOP).

Token Packets.

SOF Packet.

IN Packet.

OUT Packet.

SETUP Packet.

Data Packets—DATA0 and Data1.

Handshake Packets.

Preamble Packet.


IN Transactions.

OUT Transactions.

Setup Transactions/Control Transfers.

8. Error Recovery.


Packet Errors.

PID Checks.

CRC Errors.

Bit Stuff Errors.

Packet-Related Error Handling.

Bus Time-Out.

False EOPs.

False EOP During Host Transmission.

False EOP During Target Transmission.

Data Toggle Errors.

Data Toggle Procedure Without Errors.

Data Toggle Procedure with Data Packet Errors.

Data Toggle Procedure With Handshake Packet Errors.

Special Case. Data Toggle During Control Transfer.

Babbling Devices.

Loss of Activity (LOA).

Babble/LOA Detection and Recovery.

Frame Timer.

Host to Hub Skew.

Hub Repeater State Machine.

Isochronous Transfers (Delivery Not Guaranteed).

Interrupt Transfer Error Recovery.

Bulk Transfer Error Recovery.

Control Transfer Error Recovery.

9. USB Power Conservation.

Power Conservation—Suspend.

Device Response to Suspend.

Hub Response to Suspend.

Global Suspend.

Initiating Global Suspend.

Resume from Global Suspend.

Selective Suspend.

Initiating Selective Suspend.

Resume from Selective Suspend.

Selective Suspend When Hub is Suspended.

Selective Suspend Followed by Global Suspend.

Resume via Reset.

Hub Frame Timer After Wakeup.


10. Overview of HS Device Operation.


New High-Speed Device Features.

1.x USB Device Support.

The 2.0 Host Controller.

11. The High-Speed Signaling Environment.


Detecting High-Speed Device Attachment.

Initial Device Detection.

Device Reset and the Chirp Sequence.

High-Speed Interfaces Idled.

High-Speed Differential Signaling.

Impedance Matching.

High-Speed Driver Characteristics.

High-Speed Idle.

High-Speed Differential Receivers.

High-Speed Driver/Receiver Compliance Testing.

High-Speed Start of Packet & Synchronization Sequence.

High-Speed End of Packet (EOP).

Detection of High-Speed Device Removal.

High-Speed RESET and Suspend.

Signaling RESET.

Signaling Suspend.

Differentiating Between RESET and Suspend.

12. HS Transfers, Transactions, & Scheduling.


High-Speed Transaction Scheduling.


Theoretical HS Bandwidth.

Periodic Transfers.

High-Speed Isochronous Transfers.

High-Speed Interrupt Transfers.

High-Bandwidth Transactions.

Non-Periodic Transfers.

High-Speed Bulk Transfers.

High-Speed Control Transfers.

Ping Transactions.

13. HS Error Detection and Handling.


High-Speed Bus Time-out.

False EOP.

HS Babbling Device Detection.

14. HS Suspend and Resume.


Entering Device Suspend.

Device Resume.


15. HS Hub Overview.


USB 2.0 Hub Attached to High-Speed Port.

High-Speed Transactions.

Low- and Full-Speed Transactions.

USB 2.0 Hub Attached to Full-Speed Port.

16. 2.0 Hubs During HS Transactions.


High-Speed Hub Repeater.

Receiver Squelch.

Re-clocking the Packet.

Port Selector State Machine.

Elasticity Buffer.

The Repeater State Machine.

17. 2.0 Hubs During LS/FS Transactions.


The Structure of Split Transactions.

Isochronous Split Transaction Examples.

Example Split Transactions with Data Verification.

The Split Token Packet.

The Transaction Translator.

The Major Elements of the Transaction Translator.

Split Transaction Scheduling.

Split Transaction Scheduling Example.

Single versus Multiple Transaction Translators.

Periodic Split Transactions.

Periodic Split Transaction Pipeline.

Isochronous OUT Split Transaction Sequence.

Isochronous IN Split Transaction Sequence.

Interrupt Split OUT Transaction Sequence.

Interrupt IN Split Transaction Sequence.

Non Periodic Split Transactions.

Non-Periodic Split Transaction Pipeline.

Bulk/Control Split OUT Transaction Sequence.

Bulk/Control Split IN Transaction Sequence.


18. Configuration Process.


The Configuration Software Elements.

USB Host Controller Driver.

Configuration Software.

Default Control Pipe.

Resource Management.

Device Client Software.

Root Hub Configuration.

Each Device Is Isolated for Configuration.

Reset Forces Device to Default Address (zero).

Host Assigns a Unique Device Address.

Host Software Verifies Configuration.

Configuration Value Is Assigned.

Client Software Is Notified.

19. USB Device Configuration.


Summary of Configuration Process.

How Software Detects Device Attachment & Speed.

Polling the Status Change Endpoint.

Getting Port Status.

Resetting the Port.

Reading and Interpreting the USB Descriptors.

The Standard Descriptors.

How Software Accesses the Descriptors.

Device Descriptor.

Device Qualifier Descriptor.

Configuration Descriptors.

Other Speed Configuration Descriptor.

Interface Descriptors.

Endpoint Descriptors.

Device States.

Attached State.

Powered State.

Default State.

Addressed State.

Configured State.

Suspend State.

Client Software Configuration.

20. Hub Configuration.

Configuring the Hub.

The Default Pipe.

The Status Change Pipe.

Reading the Hub's Descriptors.

1.x Hub Descriptors.

Hub's Standard Device Descriptor.

Hub Configuration Descriptor.

Hub Interface Descriptor.

Status Endpoint Descriptor.

Hub Class Descriptor.

High-Speed Capable Hub Descriptors.

Descriptors When Hub Is Operating at Full Speed.

The 2.0 Hub's Class-Specific Descriptor.

Powering the Hub.

Checking Hub Status.

Detecting Hub Status Changes.

Reading the Hub Status Field.

Reading Port Status.

Enabling the Device.

Summary of Hub Port States.

21. Device Classes.


Device Classes.

Audio Device Class.

Standard Audio Interface Requirements.

Synchronization Types.

Audio Class-Specific Descriptors.

Audio Class-Specific Requests.

Communications Device Class.

Communications Device Interfaces.

Communications Class-Specific Descriptors.

Communications Class-Specific Requests.

Display Device Class.

The Standard Display Device Class Interface.

Display Device-Specific Descriptors.

Device-Specific Requests.

Mass Storage Device Class.

Standard Mass Storage Interface.

General Mass Storage Subclass.

CD-ROM Subclass.

Tape Subclass.

Solid State Subclass.

Class- and Device-Specific USB Requests.


22. Overview of USB Host Software.

USB Software.

Function Layer.

Device Layer.

Interface Layer.

The Software Components.

USB Driver (USBD).

Configuration Management.

USB Elements Requiring Configuration.

Allocating USB Resources.

Data Transfer Management.

Providing Client Services (The USB Driver Interface).

Pipe Mechanisms.

Command Mechanisms.


Appendix A. Standard Device Requests.


Standard Device Requests.

Set/Clear Feature.

Device Remote Wakeup.

Endpoint Stall.

Set/Get Configuration.

Set/Get Descriptor.

Set/Get Interface.

Get Status.

Device Status.

Endpoint Status.

Sync Frame.

Device Tests.

High-speed Driver/Receiver Compliance Testing.

Appendix B. Hub Requests.


Hub Request Types.

Standard Requests and Hub Response.

Hub Class Requests.

Get/Set Descriptor Request.

Get Hub Status Request.

Hub Status Fields.

Hub State Change Fields.

Set/Clear Hub Feature Request.

Hub Local Power Change Request.

Hub Over-Current Change Request.

Get Port Status Request.

Port Status Fields.

Port Change Fields.

Set/Clear Port Feature.

Port Test Modes.

Get Bus State.

Appendix C. Universal Host Controller.


Universal Host Controller Transaction Scheduling.

Universal Host Controller Frame List Access.

UHC Transfer Scheduling Mechanism.

Bus Bandwidth Reclamation.

Transfer Descriptors.

Queue Heads.

UHC Control Registers.

Appendix D. Open Host Controller.


Open Host Controller Transfer Scheduling.

The Open Host Controller Transfer Mechanism.

The ED and TD List Structure.

Interrupt Transfer Scheduling.

Endpoint Descriptors.

Transfer Descriptors.

General Transfer Descriptor.

Isochronous Transfer Descriptor.

The Open Host Controller Registers.

Index. 0201309750T04062001


The MindShare Architecture Series

The MindShare Architecture book series includes: ISA System Architecture, EISA System Architecture, 80486 System Architecture, PCI System Architecture, Pentium System Architecture, PCMCIA System Architecture, PowerPC System Architecture, Plug-and-Play System Architecture, CardBus System Architecture, Protected Mode Software Architecture, Pentium Pro and Pentium II System Architecture, USB System Architecture, FireWire System Architecture, PCI-X System Architecture, and AGP System Architecture. The book series is published by Addison-Wesley.

Rather than duplicating common information in each book, the series uses the building-block approach. ISA System Architecture is the core book upon which the others build. Table 1 on page 1 illustrates the relationship of the books to each other.

Cautionary Note

The reader should keep in mind that MindShare's book series often deals with rapidly-evolving technologies. This being the case, it should be recognized that the book is a "snapshot" of the state of the targeted technology at the time that the book was completed. We attempt to update each book on a timely basis to reflect changes in the targeted technology, but, due to various factors (waiting for the next version of the spec to be "frozen," the time necessary to make the changes, and the time to produce the books and get them out to the distribution channels), there will always be a delay.

Specifications This Book is Based On

This book is based on the Universal Serial Bus 2.0 specification.

Organization of This Book

The book is divided into six parts and contains the chapters listed below:

Part I: Overview of USB 2.0

Chapter 1: This chapter provides an overview of the primary concepts of USB transfers and describes the interaction between USB system software, system hardware, and USB devices for USB 1.x systems and USB 2.0 system. The USB communications process is described, including the concept of the device framework. Each hardware and software element in a USB system is introduced and its primary functions are described.

Chapter 2: This chapter provides an overview of the primary concepts of USB transfers and describes the interaction between USB system software, system hardware, and USB devices for USB 1.x systems and USB 2.0 system. The USB communications process is described, including the concept of the device framework. Each hardware and software element in a USB system is introduced and its primary functions are described.

Chapter 3: USB defines a single connector type for attaching all USB peripherals to the host system. This chapter introduces the physical aspects of USB connectors and cables.

Chapter 4: This chapter discusses USB power distribution, along with issues related to bus powered devices and the operation of self-powered devices. The chapter also discusses the role of host software in detecting and reporting power related problems.

Part II: The USB Solution

Chapter 5: USB employs NRZI encoding and differential signaling to transfer information across USB cables. This chapter discusses the low- and full-speed signaling environment, including the differential signaling and NRZI encoding techniques used by the USB. The signaling environment must also support a wide range of other signal-related functions such as: detecting device attachment and removal, suspending and resuming operation, resetting a device, and others all of which are discussed in this chapter.

Chapter 6: USB supports four transfer types: interrupt, bulk, isochronous, and control. These transfer types and the process used to initiate and perform them are described in this chapter.

Chapter 7: Every transfer broadcast over the USB consists of a combination of packets. These packets are combined to define individual transactions that are performed as part of a larger transfer. Each transaction type is defined, along with the individual packets that comprise them.

Chapter 8: Interrupt, Bulk, and Isochronous transfers require that the successful delivery of data be verified by USB. CRC and other error checking is performed to verify data delivery and if errors occur retries of the failed transmission are performed. This chapter discusses the various sources of errors and the error detection mechanisms used by USB to identify them, and the error recovery that is performed to overcome them.

Chapter 9: USB devices support power conservation by entering a suspended state. This chapter discusses the ways that devices are placed into the suspended state under software control. It also discusses how software re-awakens devices, and how a device such as a modem can initiate a wakeup remotely.

Part III: High Speed Device Operation

Chapter 10: This chapter provides a brief introduction to high-speed device operation and set the stage for a detailed discussion of the high-speed environment.

Chapter 11: High-speed capable devices must also be able to communicate in the full-speed signaling environment. High-speed devices add many extensions to the full-speed environment to permit reliable signaling at a 480Mb/s rate. This chapter introduces the principles associated with USB high-speed signalling and the methods used to switch between full- and high-speed operation.

Chapter 12: This chapter introduces the changes brought about by high-speed transmission rates. The transfers defined in USB 1.0 have the same primary characteristics in the high-speed environment. However, packet sizes and differences in signaling change accounts for some change. Also, new features have been added to the high-speed environment such as high-bandwidth transfers and ping protocol. These and other changes are review in this chapter.

Chapter 13: Error detection and handling during high-speed transactions is very similar in concept to the low- and full-speed error detection methods. However, due to the faster clock rates several of the timing parameters must be changed to support error detection implementations such as timout values and babble detect.

Chapter 14: This chapter discusses the changes required for high-speed devices to use the full-speed suspend and resume protocol and signaling conventions.

Part IV: USB 2.0 Hub Operation with LS/FS/HS Devices

Chapter 15: This chapter introduces the primary characteristic of a high-speed hub. It must be able to operate when attached to both full-speed and high-speed ports, and must support all device speeds on its ports.

Chapter 16: This chapter discusses the 2.0 hubs behavior when it receives high-speed packets on its upstream and downstream ports. This chapter details the operation of the high-speed repeater and discusses the delays associated with forwarding high-speed packets across the hub.

Chapter 17: This chapter introduces the concept of split transactions that allow high-speed hubs to support low- and full-speed devices without sacrificing large amounts of bus time required to access the slower devices. The operation of the transaction translator is described, along with the various forms of split transaction and the specific sequences employed by each.

Part V: USB Configuration

Chapter 18: This chapter provides an overview of the configuration process. Each of the major steps involved in USB device enumeration are defined and discussed.

Chapter 19: This chapter discusses configuration of USB devices that are attached to any USB port. The process is virtually the same for devices of any speed. Device descriptors and other characteristics and features that relate to configuring the device are also detailed and discussed.

Chapter 20: Hub devices are configured like any other device attached to a USB port. Hub configuration differs in that it involves reporting whether or not other devices are attached to the downstream ports. This chapter review the hub configuration process with the focus on the issues related to extending the bus through the hub's downstream facing ports.

Chapter 21: This chapter introduces the concept of device classes and discusses their role within the USB. This chapter discusses the first five class types that were defined. These class are discussed to provide the reader with a sense of the information defined for each class and the USB mechanisms that they use. A detailed discussion of device classes requires in-depth knowledge in the associated field such as telephony and audio.

Part VI: USB Software

Chapter 22: Host software consists of three types of components: the USB Device Drivers, the USB Driver, and the Host Controller Driver. This chapter discusses the role of each of these layers and describes the requirements of their programming interface.

Who Should Read this Book

This book is intended for use by hardware and software design and support personnel. Those individuals working outside of the design field may also find the text useful.

Prerequisite Knowledge

The reader should be familiar with PC Architectures and legacy hardware and software issues. MindShare's ISA System Architecture book provides foundation material that describes the legacy issues.

Visit Our Web Page

Our web site contains a listing of all of our courses and books. In addition, it contains errata for a number of the books, a hot link to our publisher's web site, as well as course outlines.


Our publisher's web page contains a listing or our currently-available books and includes pricing and ordering information. Their home page is accessible at:




1.x device compatibility 37
1.x devices in HS system 37, 38, 39, 40
16-bit CRC 170
2.0 host controller 40, 216
5-bit CRC 150, 170


ACK 157, 160
acknowledge packet, see ACK 153
adaptive sink 130, 131
adaptive source 131
adaptive synchronization 128
address assignment 345
alternate interfaces 365
alternate settings 364
asynchronous sink 130, 131
asynchronous source 130
asynchronous synchronization 128
attachment sequence 96
attachment sequence, HS 221
attachment timing, HS 221
attachment timing, LS/FS 96
Audio Class-Specific Descriptors 409
Audio Class-Specific Requests 410


babble 192
babbling device recovery, HS 270
babbling device recovery, LS 190
babbling devices 189
babbling devices after resume 208
babbling devices, HS 268
babbling devices, LS 189, 192
bandwidth allocation 58, 345
bandwidth allocation, bulk transfers 137
bandwidth allocation, control 137
bandwidth allocation, control transfers 121
bandwidth allocation, HS control transfers 243, 254
bandwidth allocation, HS periodic transfers 243
bandwidth allocation, LS/FS 121
bandwidth allocation, periodic transfers 121
bandwidth sharing 34
bandwidth, HS 244
bandwidth, HS interrupt 247
bit stuff errors 168
bit stuff time 428
bit stuffing 112
bit stuffing errors 170, 236
bulk transfer bandwidth 36
bulk transfer bandwidth, HS 255, 256
bulk transfers 55, 118, 137
bulk/control IN transaction sequence 332
bulk/control split transaction sequence 328
bulk/control transaction buffer 299
bus bandwidth 34, 36, 426, 428
bus bandwidth allocation 346
bus bandwidth reclamation 429
bus bandwidth sharing 34
bus bandwidth, bulk 138
bus bandwidth, HS 44
bus bandwidth, interrupt 135
bus bandwidth, isochronous 123
bus idle 102
bus idle, full speed 102
bus idle, high speed 227
bus idle, low speed 102
bus powered hubs 49
bus time-out, HS 266
bus time-out, LS/FS 172, 173
bus turn-around time 172
bus-powered device 82
bus-powered hub 80


cable cross-section, FS/HS 73
cable cross-section, LS 72
cable delay 173
cable delay, FS 107
cable length, FS & HS 73
cable length, LS 72
cable power 74
cable propagation delay, FS & HS 73
cable propagation delay, LS 72
cables 71
cables, FS & HS 73
chirp J 222
chirp K 221, 222
chirp sequence 219, 221, 223
class codes 358
class-specific descriptor 61
Clear Hub Feature request 398
Clear Hub Local Power Change 456
Clear Hub Local Power Feature request 399
Clear Hub Over-Current Change request 456
Clear Port Feature request 462
Clear Stall request 437
client driver 45
client drivers 346
client pipes 430
client software during configuration 343
command mechanisms 430, 431
Common Class Specification 407
Communication Device Class 410
Communications Class-Specific Descriptors 412
Communications Class-Specific Requests 412
Communications Device Interfaces 411
communications pipes 118, 119
Complete Split 290
complete split transaction 39
complete-split buffer 299, 312
complete-split packet format 314
composite device 358
compound device 80, 358
configuration 53
configuration descriptor 60
configuration descriptors 60, 76, 77, 359, 361, 377
configuration descriptors, hub 380
configuration sequence 340
configuration software 342
configuration software elements 341
configuration summary 348
configuration value 346, 361, 381
configuration, assigning configuration value 346
configuration, client drivers loaded 346
connection event 96
connector contacts 70
connectors 69
control transfer 136
control transfer bandwidth 36
control transfer bandwidth, HS 257
control transfer bandwidth, LS/FS 121
control transfer error recovery 193
control transfer stages 137, 163
control transfer, three stage 165
control transfer, two stage 164
control transfers 55, 118, 137, 163
control transfers with errors 166
CRC 146, 168, 169, 170
CRC16 handling, interrupt split transfers 326
CRC16 handling, isochronous split transfers 315, 319
current budget 76
current during configuration 80
current limiting 78, 81
current, per port 76
Cyclic Redundancy Check (CRC) 144


data endpoints 134
data packet errors 171
data packets 60, 143, 145, 152
data stage 137, 163
data toggle 152, 175, 253
DATA0 175
data0 packet 152
DATA0 packets 152
DATA1 175
data1 packet 152
DATA1 packets 152
DATA2 packet 253
debounce interval 97
default control endpoint 340
default control pipe 342, 376
default control port 376
default device address 345
default pipe 376, 430
depth of topology 429
descriptor 376
descriptor types 441
descriptors, accessing 354
detecting device attachment 348
device attachment 98
device attachment, high speed 219, 221
device attachment, low speed 100
device attachment, LS/FS 94
device class 366
Device class specifications 24
device configuration 340, 344, 426
device connect 96, 99
device connect, Full Speed 98
device connect, high speed 219
device descriptor 60, 355, 377
device descriptors, hub 379
device disconnect, HS 236
device disconnect, LS/FS 101
Device Framework 53, 60, 423
device layer 422
device qualifier descriptor 360
device reset 345
device states 371
Differential 0 113
Differential 1 113
differential amplifier 109
differential data 111
differential driver 106
differential envelope detector 227
differential receivers, HS 227
differential signaling 105
differential signaling, high speed 224
differential signaling, HS 227
differential signaling, LS/FS 109
disconnect envelope detector 237, 238
Display Device Class 412
Display Device Class Interface 413
Display Device-Specific Descriptors 413
DMA channel 54
DMA channels 14, 18
downstream (away from the host) 52
drain wire 72, 73
dribble bits 285


elasticity buffer 285, 286
electrical specification 74
end of frame (EOF) 190
end of packet, high speed 236
end of packet, see EOP 110, 147
endpoint 55
endpoint descriptor 61, 367, 368, 377, 428
endpoint status 443
endpoint zero 19, 340
endpoints 19
Enhanced Host Controller (EHCI) 47
Enhanced Host Controller Interface 216
enumeration 339
EOF1 190
EOF2 190, 192, 463
EOP 110, 114, 144, 147
EOP, high speed 236
EOP2 397
Error checking mechanisms 167
error recover, interrupts 135
error recovery, bulk 139
error recovery, isochronous 124
errors, packet 171
explicit feedback 134
eye diagrams 227, 231
eye diagrams, receiver 233
eye diagrams, transmitter 232
eye patterns 229


fairness 34
false EOP 174
false EOP, HS 267
feed forwarding 128, 130
feedback 128, 130, 131
feedback data 131, 133
feedback endpoints 134
frame 33, 34, 46, 47, 57, 121
frame list 30, 33
frame timer 208
full speed cable 73
full/high-speed cable cross section 73
full-speed cable length 73
full-speed cables 71, 73
full-speed devices 28, 53, 66
full-speed drivers 106
full-speed transactions 28
full-speed transmission 71
function configuration 427
function layer 65


ganged power switching 79, 387
Get Bus State request 463
Get Descriptor request 377
Get Hub Descriptor request 387, 452
Get Hub Status 456
Get Hub Status request 398, 452, 453, 455, 456
Get Port Status request 398, 399, 462
Get Status request 442
Get/Set Configuration request 440
Get/Set Descriptor request 440
Get/Set Interface request 441
global suspend 195, 197, 204


half-duplex 105
handshake packet 143
handshake packet errors 172
handshake packet formats 154
handshake packets 60, 145, 153
hardware and software elements 44
HCD 423, 424
high bandwidth isochronous 251
high speed handler 311
high/full-speed cable cross section 73
high-bandwidth 249
high-bandwidth interrupt transactions 253, 254
high-bandwidth isochronous 252
high-bandwidth isochronous transactions 254
high-bandwidth throughput 254
high-bandwidth transactions 249, 250
high-speed babbling device detection 268
high-speed bandwidth 42, 44, 243
high-speed bulk transfers 255
high-speed bus idle 227
high-speed bus time-out 266
high-speed cables 73
high-speed control transfers 257
high-speed device disconnect 236
high-speed device features 214
high-speed devices 41, 53, 66, 213, 214, 217
high-speed devices in FS system 41
high-speed devices, test mode 229
high-speed differential receivers 227
high-speed drivers 226
High-Speed End Of Packet 286
high-speed EOP 237
high-speed handler 298, 299, 328
high-speed hub repeater 284
high-speed hubs 67, 218, 278
high-speed interrupt bandwidth 247, 249
high-speed interrupt transfers 247
high-speed isochronous bandwidth 246
high-speed packets 242
high-speed port 215
high-speed reset 239
high-speed resume 273
high-speed signaling 219
high-speed suspend 239, 272
high-speed transactions 42, 242, 280
high-speed transfers 37, 243
high-speed transmission 71
host controller 47, 48
Host Controller Drive 44
host controller driver 59
host frame timing 208
host recovery time 428
hot plug 20
hub class descriptor 387
hub class descriptor (2.0) 394
hub class request 451
hub class requests 450
hub client 347
hub controller 48, 50, 51
hub delay, FS 173
hub descriptor 377
hub descriptors (2.0) 391
hub functions 48
hub low speed setup 428
hub port states 399
Hub port status information 352
hub power 76
hub repeater 52
hub repeater functions, HS 284
hub repeater state machine 191
hub repeater state matching, HS 286
hub repeater states 192
hub repeater, HS 279
hub request 448
hub requests 448
hub resume state 208
Hub Set /Clear Feature request 461
hub state change 454
hub status change endpoint 343
Hub Status Endpoint Descriptor 386
hub status fields 453
hub suspend state 196
hub types 50
hubs 49, 66, 76
hubs, FS 66
hubs, HS 67, 278, 281, 283
hub-specific requests, summary 451
Human Interface Device Class 412
hybrid powered device 89
hybrid powered hub 87
hybrid-powered 381


I/O request packet, see IRP 120
I/O Request Packets 45
idle state 104, 114
idle, high speed 223
impedance matching 224
IN 157
IN token 147
IN token packet 149
IN transaction errors 157
IN transactions 156, 157
initiating global suspend 197
input sensitivity 109
insufficient bus current 84
interface descriptor 60, 364, 377
interface descriptors, hubs 383
interface layer 423
interface number 364
Interrupt IN split transaction sequence 322
interrupt OUT split transaction sequence 319
interrupt transfer error recovery 193
interrupt transfers 55, 118, 134
interrupt transfers, HS 247
IO Hub-based host controller 25
IRP 45, 46, 57, 422, 429
IRP, see I/O request packet 120
IRQ 14, 15, 54
isochronous data endpoints 134
isochronous data packets, HS 244
Isochronous IN split transaction sequence 316
isochronous OUT split transaction sequence 313
isochronous OUT transactions 162
isochronous packet overhead, HS 245
isochronous split transactions 291, 292
isochronous transactions 34, 36, 125
isochronous transactions, HS 44
isochronous transfer 159
isochronous transfer error recovery 193
isochronous transfers 55, 118, 123
isochronous transfers, HS 244


J state 104, 113


K state 104, 114


l.x hubs 66
legacy 14
legacy connectors 17
legacy I/O 14, 16
legacy interrupts 15
LOA 192, 208
LOA error 189
local power status 453
loss of activity (LOA) 189
low- and full-speed overview 28
low speed cables 72
low speed drivers 108
low-/full-speed handler 299, 328
low-power device 82
low-speed cable 53, 71
Low-speed cable length 72
low-speed devices 28, 53, 66
low-speed packets 145
low-speed transactions 28, 154
low-speed/full-speed handler 312


Mass Storage Device Class 414
max. data packet size, bulk transfers 138
max. data packet size, control transfers 137
max. packet size, interrupt transfers 135
max. packet size, isochronous transfers 123
maximum packet size 385
maximum packet size, HS bulk 255
maximum packet size, HS interrupt 247
maximum packet size, HS isochronous 244
MaxPower field 76, 77
MDATA packet 252
mechanical specification 74
message pipes 430
microframe 46, 242, 251, 300
microframes 243
microframes generation 42
microSOF packets 237, 238, 300
multiple transaction translators 309


NAK 158, 161
No Acknowledge packet, see NAK 153
non-periodic split transaction pipeline 327
non-periodic split transactions 327
non-periodic transfers, HS 254
non-periodic TT buffers 328
non-return tozero inverted 111
NRZI 104, 111, 112, 285
number of interfaces 381


OHC Done Queue 481
OHC Endpoint Descriptors 478
OHC Interrupt Transfer Scheduling 481
OHC Transfer Descriptors 478
OHC transfer queues 481
Open Host Controller (OHC) 47, 477
Open Host Controller Driver (OHCD) 477
Open Host Controller Interface (OHCI) 30, 47
Open Host Controller Transfer Scheduling 477
other speed configuration descriptor 363
OUT token 147
OUT token packet 150
OUT transactions 150, 160
OUT transactions with errors 160
over-current protection 78, 390


packet envelope detector 285
packet errors 168
packet ID 143, 146
Packet ID (PID) checks 168
packet re-clocking 285
packet sizes 34, 36
packet sizes, HS 43
packet-related errors 171
packets 60
PCI-based host controller 25
periodic split transactions 310
periodic transaction CSbuffer 299
periodic transaction SS buffer 299
periodic transactions 36
periodic transfer bandwidth, LS/FS 121
PID check 148, 168
PING packet 263
ping protocol 261, 262
ping transactions 260
pipe mechanisms 430
pipe policy 429
plug and play 20
policy 427
polling interval 134
port change fields 459
port change indicators 456
port current, maximum 76
port current, minimum 76
port enable/disable 457
port events 99
Port Power Mask 391
port reset 103, 352
port status 350, 456
port status fields 457
port status information 352
port status register 100
port status request 351
port test 443
port test modes 462
port test selector value 463
power on to power good 390
power switching 79
power switching mode 79, 390
power verification 427
preamble packet 53, 145, 154
preamble packet format 156
propagation delay 73


re-clocking 285
remote wakeup 199, 202
remote wakeup enable/disable 439, 443
remote wakeup from global suspend 199
remote wakeup from selective suspend 202
repeater 50
repeater state machine with suspend 209
repeater state machine, HS 287
reset 103, 114, 345
RESET detection, HS 272
reset recovery 97
resource allocation 426
resource management software 343
resume 197
resume due to reset 206
resume from global suspend 198
resume from selective suspend 201
resume signaling 198
resume state 114
resume, HS 273
Root Hub 44
root hub 47
root hub configuration 343
round-trip delay, HS 266


selective resume 201, 202, 203
selective suspend 195, 201, 202, 204
self-powered device 89
self-powered hubs 86
self-powered status 442
serial interface engine (SIE) 51
series A connector 70, 71
series A plug 70
series A receptacle 70
series B connectors 70, 71
series B plug 70
series B receptacle 70
Set Address request 345
Set Configuration request 381
Set Descriptor request 452
Set Hub Local Power Change Feature 456
Set Port Enable Feature 399
Set Port Enable Feature request 344
Set Port Feature request 462
Set Port Power Feature request 387, 397
Set/Clear Feature request 439
setting the policy 427
setup stage 137, 163
SETUP token 147
SETUP token packet 151
setup token packets 151, 165
setup transactions 151, 163
signaling states, LS/FS 113
single transaction translators 309
single-ended receivers 94, 110
single-ended zero 206
sink types 129
slew rate, low speed driver 108
SOF 148, 409
SOF packets 148, 208
SOF token 147, 190
SOP 109
special packet 145
specification 24
split IN sequence 295
split OUT sequence 294
split packet format 314
SPLIT Token packet 296
split transaction scheduling 300
split transaction sequence, bulk/control IN 332
split transaction sequence, bulk/control OUT 328
split transaction sequence, interrupt IN 322
split transaction sequence, interrupt OUT 319
split transaction sequence, Isochronous IN 317
split transaction sequence, isochronous OUT 313
split transaction, CRC16 handling 315
split transactions 39, 280, 290, 293
split transactions with verification 293
split transactions, periodic 310
split-transaction pipeline, periodic transactions 311
squelch 227, 283, 285
STALL 159, 162
Stall packet, see STALL 153
standard descriptor types 354
standard descriptors 19, 353, 377
standard device request types 436
standard requests, hubs 449
start of frame (SOF) 46
Start of High-Speed Packet 286
start of packet (SOP) 114
start of packet, see SOP 109
Start Split 290
start split transaction 39
start-split buffer 299, 312
start-split packet format 314
start-split packet types 314
start-split transaction example 301
start-split transactions, periodic 311
status change endpoint 344, 349, 376, 384
status stage 137, 163
stream pipes 430
string descriptor 61, 359, 377
stuffed bits, see bit stuffing 170
subclass 366
suspend 23, 195
suspend detection, HS 272
suspend state 196
suspend, HS 239, 272
Sync Frame request 444
synchronization sequence 144
synchronization sequence, HS 227, 234, 235, 242
synchronization types 128, 131, 409
synchronous connections 125, 128, 130, 131
synchronous data 125
synchronous sink 130, 131
synchronous source 130
synchronous streams 125
synchronous sychronization 128
syncrhonization sequence 109


test mode activation 444
test mode, HS devices 229
test packet 232
test selector values 445
The Universal Host Controller (UHC) 465
tiered star topology 67
token packet errors 171
token packets 60, 143, 145, 147
topology 67
topology, HS 282
transaction generation 30, 31, 32
transaction list 30
transaction scheduling, HS 242
transaction translator 277, 279, 289, 297, 298, 310
transaction translators, single or multiple 309, 310
transfer descriptor contents 30, 54
transfer descriptors 30, 31, 33, 42, 47, 54, 59
transfer types 55, 122, 385
transmission envelope detector 235


UHC bus bandwidth reclamation 468
UHC Control Registers 476
UHC frame list 466
UHC queue heads 473
UHC transfer descriptors 465
UHC Transfer Scheduling 467
Univeral Serial Bus (USB) 19
Universal Host Controller Driver (UHCD) 465
Universal Host Controller Interface (UHCI) 30, 47
upstream (toward the host) 52
USB 1.x systems 213
USB 2.0 specification 74
USB 2.0 systems 213
USB 2.0 systems and device overview 37
USB bandwidth 57
USB bus driver 45, 46
USB bus interface layer 63
USB client drivers 46, 424
USB configuration 426
USB connectors 69
USB device configuration 340
USB Device Drivers 44
USB device drivers 45
USB device layer 64
USB Driver 44, 59, 65, 424, 426, 428, 430
USB driver 55
USB enumeration 339
USB enumerator 387
USB features 23
USB host controller 25
USB host controller driver 46, 65
USB host controller driver (HCD) 46
USB hub 49
USB hubs 44
USB ports 49
USB resource allocation 345
USB specification 24
USB system software 65
USB transfer 54
USB web site 24
USBD 424


voltage drop budget 78




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