Universal Serial Bus System Architecture, Second Edition, based on the 2.0 version of the Universal Serial Bus specification, provides in-depth coverage and a detailed discussion of USB. It focuses on the USB protocol, signaling environment, and electrical specifications, along with the hardware/software interaction required to configure and access USB devices. Key topics include:
This second edition has been updated to reflect the changes in the USB specification from the original 1.0 to the current 2.0. The USB 2.0 specification defines high-speed transactions operating at 480Mb/s that increase throughput by a factor of 40 over the older USB devices. New high-bandwidth, ping, and split transactions have also been added to further increase efficiency of the high-speed protocol. The USB 2.0 specification makes major improvements to USB, while maintaining backward compatibility with 1.0 and 1.1 USB devices. If you design or test hardware or software that involves USB, you wouldn't want to miss the important updates in this book. Universal Serial Bus System Architecture, Second Edition, is an essential, time-saving tool.
The accompanying CD-ROM includes an 85-minute USB 2.0 overview video by Don Anderson, featuring an introduction to the basic concepts underlying USB 2.0 bus operation and protocol. Topics covered include terminology, design goals of USB, a review of low- and full-speed operation used by USB 1.0 and 1.1 systems and devices, an introduction to USB 2.0 high-speed transfers, and how USB 2.0 hubs use split transactions to provide backward compatibility to low- and full-speed devices.
The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title is designed to illustrate the relationship between the software and hardware and explains thoroughly the architecture, features, and operations of systems built using one particular type of chip or hardware specification.
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About This Book.
The MindShare Architecture Series.
Specifications This Book is Based On.
Organization of This Book.
Who Should Read this Book.
Identification of Bit Fields (logical groups of bits or signals).
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I. OVERVIEW OF USB 2.0.1. Design Goals of USB.
Shortcomings of the Original PC I/O Paradigm.
Limited System Resources.
End User Concerns.
The USB Paradigm.
Enhanced System Performance.
Hot Plug and Play Support.
Legacy Hardware/Software Support.
Summary of Key USB Features.
How to Get the USB Specifications.2. The Big Picture.
USB 1.x Systems and Devices.
Low-Speed and Full-Speed Devices.
How Transactions Are Generated.
Sharing the Bus.
Bandwidth Consideration Summary.
2.0 Systems and Devices.
Low-Speed and Full-Speed Devices in a 2.0 System.
High-Speed Devices in a 2.0 System.
High-Speed Bandwidth Summary.
USB Client Drivers.
USB Bus Driver.
USB Host Controller Driver.
USB Host Controller/Root Hub.
USB Communications Model.
Transfers, IRPs, Frames, and Packets.
Device Framework (how devices present themselves to software).
USB Peripheral Connection.
Topology.3. Cables and Connectors.
Series A Connectors.
Series B Connectors.
Full- and High-Speed Cables.
Electrical and Mechanical Specifications.4. USB Cable Power Distribution.
Voltage Drop Budget.
Power During Hub Configuration.
Bus-Powered Hub Attached to 500ma Port.
Bus-Powered Hub Attached to 100ma Port.
Bus-Powered Hub Attached to Port with >100ma but <500ma.
Power During Configuration.
Power During Configuration.
II. LOW- & FULL-SPEED DEVICE OPERATION.5. LS/FS Signaling Environment.
Detecting Device Attachment and Speed Detect.
Full-Speed Device Connect.
Low-Speed Device Connect.
Detecting Device Disconnect.
Start of Packet (SOP).
End of Packet (EOP).
Summary of USB Signaling States.6. LS/FS Transfer Types & Scheduling.
Client Initiates Transfer.
Communication Initiated by I/O Request Packets.
Establishing Synchronous Connections.
The Feedback/Feed Forwarding Solution.
Bulk Transfers.7. Packets & Transactions.
Packets—The Basic Building Blocks of USB Transactions.
Cyclic Redundancy Checking (CRC).
End of Packet (EOP).
Data Packets—DATA0 and Data1.
Setup Transactions/Control Transfers.8. Error Recovery.
Bit Stuff Errors.
Packet-Related Error Handling.
False EOP During Host Transmission.
False EOP During Target Transmission.
Data Toggle Errors.
Data Toggle Procedure Without Errors.
Data Toggle Procedure with Data Packet Errors.
Data Toggle Procedure With Handshake Packet Errors.
Special Case. Data Toggle During Control Transfer.
Loss of Activity (LOA).
Babble/LOA Detection and Recovery.
Host to Hub Skew.
Hub Repeater State Machine.
Isochronous Transfers (Delivery Not Guaranteed).
Interrupt Transfer Error Recovery.
Bulk Transfer Error Recovery.
Control Transfer Error Recovery.9. USB Power Conservation.
Device Response to Suspend.
Hub Response to Suspend.
Initiating Global Suspend.
Resume from Global Suspend.
Initiating Selective Suspend.
Resume from Selective Suspend.
Selective Suspend When Hub is Suspended.
Selective Suspend Followed by Global Suspend.
Resume via Reset.
Hub Frame Timer After Wakeup.
III. HIGH SPEED DEVICE OPERATION.10. Overview of HS Device Operation.
New High-Speed Device Features.
1.x USB Device Support.
The 2.0 Host Controller.11. The High-Speed Signaling Environment.
Detecting High-Speed Device Attachment.
Initial Device Detection.
Device Reset and the Chirp Sequence.
High-Speed Interfaces Idled.
High-Speed Differential Signaling.
High-Speed Driver Characteristics.
High-Speed Differential Receivers.
High-Speed Driver/Receiver Compliance Testing.
High-Speed Start of Packet & Synchronization Sequence.
High-Speed End of Packet (EOP).
Detection of High-Speed Device Removal.
High-Speed RESET and Suspend.
Differentiating Between RESET and Suspend.12. HS Transfers, Transactions, & Scheduling.
High-Speed Transaction Scheduling.
Theoretical HS Bandwidth.
High-Speed Isochronous Transfers.
High-Speed Interrupt Transfers.
High-Speed Bulk Transfers.
High-Speed Control Transfers.
Ping Transactions.13. HS Error Detection and Handling.
High-Speed Bus Time-out.
HS Babbling Device Detection.14. HS Suspend and Resume.
Entering Device Suspend.
IV. USB 2.0 HUB OPERATION WITH LS/FS/HS DEVICES.15. HS Hub Overview.
USB 2.0 Hub Attached to High-Speed Port.
Low- and Full-Speed Transactions.
USB 2.0 Hub Attached to Full-Speed Port.16. 2.0 Hubs During HS Transactions.
High-Speed Hub Repeater.
Re-clocking the Packet.
Port Selector State Machine.
The Repeater State Machine.17. 2.0 Hubs During LS/FS Transactions.
The Structure of Split Transactions.
Isochronous Split Transaction Examples.
Example Split Transactions with Data Verification.
The Split Token Packet.
The Transaction Translator.
The Major Elements of the Transaction Translator.
Split Transaction Scheduling.
Split Transaction Scheduling Example.
Single versus Multiple Transaction Translators.
Periodic Split Transactions.
Periodic Split Transaction Pipeline.
Isochronous OUT Split Transaction Sequence.
Isochronous IN Split Transaction Sequence.
Interrupt Split OUT Transaction Sequence.
Interrupt IN Split Transaction Sequence.
Non Periodic Split Transactions.
Non-Periodic Split Transaction Pipeline.
Bulk/Control Split OUT Transaction Sequence.
Bulk/Control Split IN Transaction Sequence.
V. USB DEVICE CONFIGURATION.18. Configuration Process.
The Configuration Software Elements.
USB Host Controller Driver.
Default Control Pipe.
Device Client Software.
Root Hub Configuration.
Each Device Is Isolated for Configuration.
Reset Forces Device to Default Address (zero).
Host Assigns a Unique Device Address.
Host Software Verifies Configuration.
Configuration Value Is Assigned.
Client Software Is Notified.19. USB Device Configuration.
Summary of Configuration Process.
How Software Detects Device Attachment & Speed.
Polling the Status Change Endpoint.
Getting Port Status.
Resetting the Port.
Reading and Interpreting the USB Descriptors.
The Standard Descriptors.
How Software Accesses the Descriptors.
Device Qualifier Descriptor.
Other Speed Configuration Descriptor.
Client Software Configuration.20. Hub Configuration.
Configuring the Hub.
The Default Pipe.
The Status Change Pipe.
Reading the Hub's Descriptors.
1.x Hub Descriptors.
Hub's Standard Device Descriptor.
Hub Configuration Descriptor.
Hub Interface Descriptor.
Status Endpoint Descriptor.
Hub Class Descriptor.
High-Speed Capable Hub Descriptors.
Descriptors When Hub Is Operating at Full Speed.
The 2.0 Hub's Class-Specific Descriptor.
Powering the Hub.
Checking Hub Status.
Detecting Hub Status Changes.
Reading the Hub Status Field.
Reading Port Status.
Enabling the Device.
Summary of Hub Port States.21. Device Classes.
Audio Device Class.
Standard Audio Interface Requirements.
Audio Class-Specific Descriptors.
Audio Class-Specific Requests.
Communications Device Class.
Communications Device Interfaces.
Communications Class-Specific Descriptors.
Communications Class-Specific Requests.
Display Device Class.
The Standard Display Device Class Interface.
Display Device-Specific Descriptors.
Mass Storage Device Class.
Standard Mass Storage Interface.
General Mass Storage Subclass.
Solid State Subclass.
Class- and Device-Specific USB Requests.
VI. USB SOFTWARE OVERVIEW.22. Overview of USB Host Software.
The Software Components.
USB Driver (USBD).
USB Elements Requiring Configuration.
Allocating USB Resources.
Data Transfer Management.
Providing Client Services (The USB Driver Interface).
VII. APPENDIX.Appendix A. Standard Device Requests.
Standard Device Requests.
Device Remote Wakeup.
High-speed Driver/Receiver Compliance Testing.Appendix B. Hub Requests.
Hub Request Types.
Standard Requests and Hub Response.
Hub Class Requests.
Get/Set Descriptor Request.
Get Hub Status Request.
Hub Status Fields.
Hub State Change Fields.
Set/Clear Hub Feature Request.
Hub Local Power Change Request.
Hub Over-Current Change Request.
Get Port Status Request.
Port Status Fields.
Port Change Fields.
Set/Clear Port Feature.
Port Test Modes.
Get Bus State.Appendix C. Universal Host Controller.
Universal Host Controller Transaction Scheduling.
Universal Host Controller Frame List Access.
UHC Transfer Scheduling Mechanism.
Bus Bandwidth Reclamation.
UHC Control Registers.Appendix D. Open Host Controller.
Open Host Controller Transfer Scheduling.
The Open Host Controller Transfer Mechanism.
The ED and TD List Structure.
Interrupt Transfer Scheduling.
General Transfer Descriptor.
Isochronous Transfer Descriptor.
The Open Host Controller Registers.Index. 0201309750T04062001
The MindShare Architecture book series includes: ISA System Architecture, EISA System Architecture, 80486 System Architecture, PCI System Architecture, Pentium System Architecture, PCMCIA System Architecture, PowerPC System Architecture, Plug-and-Play System Architecture, CardBus System Architecture, Protected Mode Software Architecture, Pentium Pro and Pentium II System Architecture, USB System Architecture, FireWire System Architecture, PCI-X System Architecture, and AGP System Architecture. The book series is published by Addison-Wesley.
Rather than duplicating common information in each book, the series uses the building-block approach. ISA System Architecture is the core book upon which the others build. Table 1 on page 1 illustrates the relationship of the books to each other.
The reader should keep in mind that MindShare's book series often deals with rapidly-evolving technologies. This being the case, it should be recognized that the book is a "snapshot" of the state of the targeted technology at the time that the book was completed. We attempt to update each book on a timely basis to reflect changes in the targeted technology, but, due to various factors (waiting for the next version of the spec to be "frozen," the time necessary to make the changes, and the time to produce the books and get them out to the distribution channels), there will always be a delay.
This book is based on the Universal Serial Bus 2.0 specification.
The book is divided into six parts and contains the chapters listed below:
Chapter 1: This chapter provides an overview of the primary concepts of USB transfers and describes the interaction between USB system software, system hardware, and USB devices for USB 1.x systems and USB 2.0 system. The USB communications process is described, including the concept of the device framework. Each hardware and software element in a USB system is introduced and its primary functions are described.
Chapter 2: This chapter provides an overview of the primary concepts of USB transfers and describes the interaction between USB system software, system hardware, and USB devices for USB 1.x systems and USB 2.0 system. The USB communications process is described, including the concept of the device framework. Each hardware and software element in a USB system is introduced and its primary functions are described.
Chapter 3: USB defines a single connector type for attaching all USB peripherals to the host system. This chapter introduces the physical aspects of USB connectors and cables.
Chapter 4: This chapter discusses USB power distribution, along with issues related to bus powered devices and the operation of self-powered devices. The chapter also discusses the role of host software in detecting and reporting power related problems.
Chapter 5: USB employs NRZI encoding and differential signaling to transfer information across USB cables. This chapter discusses the low- and full-speed signaling environment, including the differential signaling and NRZI encoding techniques used by the USB. The signaling environment must also support a wide range of other signal-related functions such as: detecting device attachment and removal, suspending and resuming operation, resetting a device, and others all of which are discussed in this chapter.
Chapter 6: USB supports four transfer types: interrupt, bulk, isochronous, and control. These transfer types and the process used to initiate and perform them are described in this chapter.
Chapter 7: Every transfer broadcast over the USB consists of a combination of packets. These packets are combined to define individual transactions that are performed as part of a larger transfer. Each transaction type is defined, along with the individual packets that comprise them.
Chapter 8: Interrupt, Bulk, and Isochronous transfers require that the successful delivery of data be verified by USB. CRC and other error checking is performed to verify data delivery and if errors occur retries of the failed transmission are performed. This chapter discusses the various sources of errors and the error detection mechanisms used by USB to identify them, and the error recovery that is performed to overcome them.
Chapter 9: USB devices support power conservation by entering a suspended state. This chapter discusses the ways that devices are placed into the suspended state under software control. It also discusses how software re-awakens devices, and how a device such as a modem can initiate a wakeup remotely.
Chapter 10: This chapter provides a brief introduction to high-speed device operation and set the stage for a detailed discussion of the high-speed environment.
Chapter 11: High-speed capable devices must also be able to communicate in the full-speed signaling environment. High-speed devices add many extensions to the full-speed environment to permit reliable signaling at a 480Mb/s rate. This chapter introduces the principles associated with USB high-speed signalling and the methods used to switch between full- and high-speed operation.
Chapter 12: This chapter introduces the changes brought about by high-speed transmission rates. The transfers defined in USB 1.0 have the same primary characteristics in the high-speed environment. However, packet sizes and differences in signaling change accounts for some change. Also, new features have been added to the high-speed environment such as high-bandwidth transfers and ping protocol. These and other changes are review in this chapter.
Chapter 13: Error detection and handling during high-speed transactions is very similar in concept to the low- and full-speed error detection methods. However, due to the faster clock rates several of the timing parameters must be changed to support error detection implementations such as timout values and babble detect.
Chapter 14: This chapter discusses the changes required for high-speed devices to use the full-speed suspend and resume protocol and signaling conventions.
Chapter 15: This chapter introduces the primary characteristic of a high-speed hub. It must be able to operate when attached to both full-speed and high-speed ports, and must support all device speeds on its ports.
Chapter 16: This chapter discusses the 2.0 hubs behavior when it receives high-speed packets on its upstream and downstream ports. This chapter details the operation of the high-speed repeater and discusses the delays associated with forwarding high-speed packets across the hub.
Chapter 17: This chapter introduces the concept of split transactions that allow high-speed hubs to support low- and full-speed devices without sacrificing large amounts of bus time required to access the slower devices. The operation of the transaction translator is described, along with the various forms of split transaction and the specific sequences employed by each.
Chapter 18: This chapter provides an overview of the configuration process. Each of the major steps involved in USB device enumeration are defined and discussed.
Chapter 19: This chapter discusses configuration of USB devices that are attached to any USB port. The process is virtually the same for devices of any speed. Device descriptors and other characteristics and features that relate to configuring the device are also detailed and discussed.
Chapter 20: Hub devices are configured like any other device attached to a USB port. Hub configuration differs in that it involves reporting whether or not other devices are attached to the downstream ports. This chapter review the hub configuration process with the focus on the issues related to extending the bus through the hub's downstream facing ports.
Chapter 21: This chapter introduces the concept of device classes and discusses their role within the USB. This chapter discusses the first five class types that were defined. These class are discussed to provide the reader with a sense of the information defined for each class and the USB mechanisms that they use. A detailed discussion of device classes requires in-depth knowledge in the associated field such as telephony and audio.
Chapter 22: Host software consists of three types of components: the USB Device Drivers, the USB Driver, and the Host Controller Driver. This chapter discusses the role of each of these layers and describes the requirements of their programming interface.
This book is intended for use by hardware and software design and support personnel. Those individuals working outside of the design field may also find the text useful.
The reader should be familiar with PC Architectures and legacy hardware and software issues. MindShare's ISA System Architecture book provides foundation material that describes the legacy issues.
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