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Superscalar Microprocessors Design

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Superscalar Microprocessors Design


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  • concentrates mostly on reduced-instruction-set (RISC) processors, but gives some attention to complex-instruction-set (CISC) processors.
  • begins by showing how superscalar processors relate to other architectural organizations, highlighting the unique characteristics of general-purpose microprocessors, and how these characteristics affect design decisions.
  • explores implementation alternatives, using a superscalar model of the MIPS R2000 architecture.
  • uses measurements of real applications programs to evaluate cost/performance trade-offs of many different hardware alternatives.
  • covers compiler optimizations, describes the basic techniques and algorithms used, and examines hardware in the light of software optimizations.
  • summarizes the potential for technical and commercial development of superscalar microprocessors.


  • Copyright 1991
  • Dimensions: 7" x 9-1/4"
  • Pages: 312
  • Edition: 1st
  • Book
  • ISBN-10: 0-13-875634-1
  • ISBN-13: 978-0-13-875634-5

The term superscalar describes a computer architecture that achieves performance by concurrent execution of scalar instructions. Superscalar architectures represent the next step in the evolution of microprocessors. This book is intended as a technical tutorial and introduction for engineers & computer scientists. The book concentrates on reduced instruction set (RISC) processors.

Sample Content

Table of Contents

 1. Beyond Pipelining, CISC, and RISC.

 2. An Introduction to Superscalar Concepts.

 3. Developing an Execution Model.

 4. Instruction Fetching and Decoding.

 5. The Role of Exception Recovery.

 6. Register Dataflow.

 7. Out-of-Order Instruction Execution.

 8. Memory Dataflow.

 9. Complexity and Controversy.

10. Basic Software Scheduling.

11. Software Scheduling Across Branches.

12. Evaluating Alternatives: A Perspective on Superscalar Microprocessors.



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