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  • Provides the only complete single-volume reference for SPICE modeling in solid state electronics.
  • Reviews the basic physics of semiconductor devices and the standard forms for modeling and testing them, along with a comparison of analytical and numerical results.
  • Discusses these major FET models:
    • Levels 1, 2, and 3

    • BSIM, BSIM2, and BSIMI3

    • HSPICE Level 28

    • MOS Model 9.

  • The book also discusses device capacitance, process variations, and the correlation of various models with specific hardware, then looks to the future of device models for circuit simulation.
  • Appendices include a comparative overview of the models discussed, a review of channel layout, and a full listing of all of the model equations.


  • Copyright 1997
  • Dimensions: 7" x 9-1/4"
  • Pages: 672
  • Edition: 1st
  • Book
  • ISBN-10: 0-13-227935-5
  • ISBN-13: 978-0-13-227935-2

This book will help CMOS circuit designers make the best possible use of SPICE models, and will prepare them for new models that may soon be introduced.KEY TOPICS:Introduces SPICE modeling and its use in CMOS circuit design. Presents the formalism of model building and the semiconductor physics of MOS structures. Covers each important SPICE model, showing how to choose the appropriate model. Discusses the popular HSPICE Level 28, as well as Levels 1-3, BSIM 1-3, and MOS Model 9. Presents techniques for accounting for systematic process variations. Describes new model candidates, including the Power-Lane Model, the PCIM Model, and the EKV Model. Includes extensive examples throughout.MARKET:Practicing engineers and scientists in the semiconductor industry; engineering faculty and students.

Sample Content

Table of Contents

 1. SPICE Modeling and the Dominance of CMOS Technology.

 2. SPICE Modeling and the Formalism of Model Building.

 3. The Semiconductor Physics of MOS Structures.

 4. A Comparison of Analytical and Numerical Results.

 5. The Level 1 Model.

 6. The Level 2 Model.

 7. The Level 3 Model.

 8. BSIM.

 9. HSPICE Level 28.

10. BSIM2.

11. BSIM3.

12. MOS Model 9.

13. The Active Device Capacitance.

14. Accounting for Systematic Process Variations.

15. Circuit Level Correlation of Models and Hardware.

16. New Model Candidates.

17. The Future of Device Models for Circuit Simulation.


 A. An Executive Summary of the Various Models.
 B. Channel Length and Width.
 C. The Final Model Equations.
 D. The Extracted HSPICE Level 28 Model.
 E. The Binned BSIM2 Model.



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