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Guide to VHDL Syntax, A

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Guide to VHDL Syntax, A


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  • describes the complete syntax of the latest version of the language — IEEE Standard 1076, 1993.
  • addresses all the constructs of the language — one major construct per section, with examples of many different forms of its use.
  • presents the syntax of all sub-constructs, down to such basics as identifiers and expressions, within the same section.
  • explains the predefined environment in VHDL, with many examples of the predefined attributes. Describes the contents of packages STANDARD and TEXTIO.
  • explores the new features in the VHDL'93 version of the language as compared to VHDL '87, and highlights features in VHDL '87 that are not portable to VHDL '93.
  • lists all major constructs in the Table of Contents and cross-references all major and minor constructs in the Index for quick reference.


  • Copyright 1995
  • Dimensions: 6" x 9"
  • Pages: 288
  • Edition: 1st
  • Book
  • ISBN-10: 0-13-324351-6
  • ISBN-13: 978-0-13-324351-2

VHDL is clearly becoming the defacto standard as an electronic hardware description language — yet the bible of VHDL, the large and complex Language Reference Manual (LRM), is exceptionally cumbersome, if not difficult, to use — various parts of the syntax for major constructs are spread in disparate sections throughout the Manual. Designed to alleviate such problems and frustrations, this guide describes the complete syntax of the IEEE Std 1076-1993 version of VHDL — showing the complete syntax of major VHDL constructs and sub-constructs in an easy-to-read manner, with clear examples of each. MARKET: A reference for anyone writing VHDL models or using VHDL in CAD development.

Sample Content

Table of Contents

1. Introduction.

2. Syntax Guide.

3. Predefined Environment.

4. Changes from VHDL '87.




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