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Design-For-Test For Digital IC's and Embedded Core Systems

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Design-For-Test For Digital IC's and Embedded Core Systems


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  • Copyright 1999
  • Dimensions: 7" x 9-1/4"
  • Pages: 384
  • Edition: 1st
  • Book
  • ISBN-10: 0-13-084827-1
  • ISBN-13: 978-0-13-084827-7


The first practical DFT guide from an industry insider.

Skip the high-brow theories and mathematical formulas—get down to the business of digital design and testing as it's done in the real world. Learn practical testing strategies that address today's business needs for quality, reliability, and cost control, working within the tight deadlines of typical high-pressure production environments. Design-for-Test for Digital IC's and Embedded Core Systems helps you optimize the engineering trade-offs between such resources as silicon area, operating frequency, and power consumption, while balancing the corporate concerns of cost-of-test, time-to-market, and time-to-volume. You'll also boost your efficiency with the special focus on automatic test pattern generation (ATPG).

The book includes a roadmap that allows you to fine-tune your learning if you want to skip directly to a specific subject. Key topics include:

  • Core-based design, focusing on embedded cores and embedded memories
  • System-on-a-chip and ultra-large scale integrated design issues
  • AC scan, at-speed scan, and embedded DFT
  • Built-in self-test, including memory BIST, logic BIST, and scan BIST
  • Virtual test sockets and testing in isolation
  • Design for reuse, including reuse vectors and cores
  • Test issues being addressed by VSIA and the IEEE P1500 Standard

Design-for-Test for Digital IC's and Embedded Core Systems is filled with full-page graphics taken directly from the author's teaching materials. Every section is illustrated with flow-charts, engineering diagrams, and conceptual summaries to make learning and reference fast and easy. This book is a must for the engineers and managers involved in design and testing.

The enclosed CD-ROM contains full-color versions of all the book's illustrations in Acrobat PDF format. These images may be viewed interactively on screen or printed out to create overheads for teaching. Acrobat Reader software for Windows and UNIX computers is included.


CD Contents

Files from the accompanying CD can be downloaded here.

Sample Content

Downloadable Sample Chapter

Click here for a sample chapter for this book: 0130848271.pdf

Table of Contents




1. Test and Design-for-Test Fundamentals.

Introduction to Test and DFT Fundamentals.

Purpose. Introduction to Test, the Test Process, and Design-for-Test. Concurrent Test Engineering.

The Reasons for Testing.

Why Test? Why Add Test Logic? Pro and Con Perceptions of DFT.

The Definition of Testing.

What Is Testing? Stimulus. Response.

Test Measurement Criteria.

What Is Measured? Fault Metric Mathematics.

Fault Modeling.

Physical Defects. Fault Modeling.

Types of Testing.

Functional Testing. Structural Testing. Combinational Exhaustive and Pseudo-Exhaustive Testing. Full Exhaustive Testing. Test Styles.

Manufacturing Test.

The Manufacturing Test Process. Manufacturing Test Load Board. Manufacturing Test Program.

Using Automatic Test Equipment.

Automatic Test Equipment. ATE Limitations. ATE Cost Considerations.

Test and Pin Timing.

Tester and Device Pin Timing. Tester Edge Sets. Tester Precision and Accuracy.

Manufacturing Test Program Components.

The Pieces and Parts of a Test Program. Test Program Optimization.

Recommended Reading.

2. Automatic Test Pattern Generation Fundamentals.

Introduction to Automatic Test Pattern Generation.

Purpose. Introduction to Automated Test Pattern Generation. The Vector Generation Process Flow.

The Reasons for ATPG.

Why ATPG? Pro and Con Perceptions of ATPG.

The Automatic Test Pattern Generation Process.

Introduction to ATPG.

Introducing the Combinational Stuck-At Fault.

Combinational Stuck-At Faults. Combinational Stuck-At Fault Detection.

Introducing the Delay Fault.

Delay Faults. Delay Fault Detection.

Introducing the Current-Based Fault.

Current-Based Testing. Current-Based Testing Detection.

Testability and Fault Analysis Methods.

Why Conduct ATPG Analysis or Testability Analysis? What Types of Testability Analysis Are Available? Fault Effective Circuits. Controllability-Observability Analysis. Circuit Learning.

Fault Masking.

Causes and Effects of Fault Masking. Fault Masking on Various Fault Models.

Stuck Fault Equivalence.

Fault Equivalence Optimization. Fault Equivalence Side Effects.

Stuck-At ATPG.

Fault Selection. Exercising the Fault. Detect Path Sensitization.

Transition Delay Fault ATPG.

Using ATPG with Transition Delay Faults. Transition Delay Is a Gross Delay Fault.

Path Delay Fault ATPG.

Path Delay ATPG. Robust Fault Detection. The Path Delay Design Description. Path Enumeration.

Current-Based Fault ATPG.

Current-Based ATPG Algorithms.

Combinational versus Sequential ATPG.

Multiple Cycle Sequential Test Pattern Generation. Multiple Time Frame Combinational ATPG. Two-Time-Frame ATPG Limitations. Cycle-Based ATPG Limitations.

Vector Simulation.

Fault Simulation. Simulation for Manufacturing Test.

ATPG Vectors.

Vector Formats. Vector Compaction and Compression.

ATPG-Based Design Rules.

The ATPG Tool "NO" Rules List. Exceptions to the Rules.

Selecting an ATPG Tool.

The Measurables. The ATPG Benchmark Process.

ATPG Fundamentals Summary.

Establishing an ATPG Methodology.

Recommended Reading.

3. Scan Architectures and Techniques.

Introduction to Scan-Based Testing.

Purpose. The Testing Problem. Scan Testing. Scan Testing Misconceptions.

Functional Testing. The Scan Effective Circuit. The Mux-D Style Scan Flip-Flops.

The Multiplexed-D Flip-Flop Scan Cell. Perceived Silicon Impact of the Mux-D Scan Flip-Flop. Other Types of Scan Flip-Flops. Mixing Scan Styles.

Preferred Mux-D Scan Flip-Flops.

Operation Priority of the Multiplexed-D Flip-Flop Scan Cell. The Mux-D Flip-Flop Family.

The Scan Shift Register or Scan Chain.

The Scan Architecture for Test. The Scan Shift Register (a.k.a The Scan Chain).

Scan Cell Operations.

Scan Cell Transfer Functions.

Scan Test Sequencing. Scan Test Timing. Safe Scan Shifting. Safe Scan Sampling: Contention-Free Vectors.

Contention-Free Vectors.

Partial Scan.

Scan Testing with Partial-Scan. Sequential ATPG.

Multiple Scan Chains.

Advantages of Multiple Scan Chains. Balanced Scan Chains.

The Borrowed Scan Interface.

Setting up a Borrowed Scan Interface. The Shared Scan Input Interface. The Shared Scan Output Interface.

Clocking, On-Chip Clock Sources, and Scan.

On-Chip Clock Sources and Scan Testing. On-Chip Clocks and Being Scan Tested.

Scan-Based Design Rules.

Scan-Based DFT and Design Rules. The Rules.

Stuck-At (DC) Scan Insertion.

DC Scan Insertion. Extras. DC Scan Insertion and Multiple Clock Domains.

Stuck-At Scan Diagnostics.

Implementing Stuck-At Scan Diagnostics. Diagnostic Fault Simulation. Functional Scan-Out.

At-Speed Scan (AC) Test Goals.

AC Test Goals. Cost Drivers.

At-Speed Scan Testing.

Uses of At-Speed Scan Testing. At-Speed Scan Sequence. At-Speed Scan versus DC Scan.

The At-Speed Scan Architecture.

At-Speed Scan Interface. At-Speed "Safe Shifting" Logic. At-Speed Scan Sample Architecture.

The At-Speed Scan Interface.

At-Speed Scan Shift Interface. At-Speed Scan Sample Interface.

Multiple Clock and Scan Domain Operation.

Multiple Timing Domains.

Scan Insertion and Clock Skew.

Multiple Clock Domains, Clock Skew, and Scan Insertion. Multiple Time Domain Scan Insertion.

Scan Insertion for At-Speed Scan.

Scan Cell Substitution. Scan Control Signal Insertion. Scan Interface Insertion. Other Considerations.

Critical Paths for At-Speed Scan.

Critical Paths. Critical Path Selection. Path Filtering. False Path Content. Real Critical Paths. Critical Path Scan-Based Diagnostics.

Scan-Based Logic BIST.

Pseudo-Random Pattern Generation. Signature Analysis. Logic Built-In Self-Test. LFSR Science (A Quick Tutorial). X-Management. Abasing.

Scan Test Fundamentals Summary. Recommended Reading.

4. Memory Test Architectures and Techniques.

Introduction to Memory Testing.

Purpose. Introduction to Memory Test.

Types of Memories.

Categorizing Memory Types.

Memory Organization.

Types of Memory Organization.

Memory Design Concerns.

Trade-Offs in Memory Design.

Memory Integration Concerns.

Key Issues in Memory Integration.

Embedded Memory Testing Methods.

Memory Test Methods and Options.

The Basic Memory Testing Model.

Memory Testing. Memory Test Fault Model. Memory Test Failure Modes.

The Stuck-At Bit-Cell Based Fault Models.

Stuck-At Based Memory Bit-Cell Fault Models. Stuck-At Fault Exercising and Detection.

The Bridging Defect-Based Fault Models.

Bridging Defect-Based Memory Test Fault Models. Linking Defect Memory Test Fault Models. Bridging Fault Exercising and Detection.

The Decode Fault Model.

Memory Decode Fault Models. Decode Fault Exercising and Detection.

The Data Retention Fault.

Memory Test Data Retention Fault Models. DRAM Refresh Requirements.

Diagnostic Bit Mapping.

Memory Test Diagnostics: Bit Mapping.

Algorithmic Test Generation.

Introduction to Algorithmic Test Generation. Automatic Test Generation. BIST-Based Algorithmic Testing.

Memory Interaction with Scan Testing.

Scan Test Considerations. Memory Interaction Methods. Input Observation. Output Control.

Scan Test Memory Modeling.

Modeling the Memory for ATPG Purposes. Limitations.

Scan Test Memory Black-Boxing.

The Memory Black-Boxing Technique. Limitations and Concerns.

Scan Test Memory Transparency.

The Memory Transparency Technique. Limitations and Concerns.

Scan Test Memory Model of The Fake Word.

The Fake Word Technique. Limitations and Concerns.

Memory Test Requirements for MBIST.

Memory Test Organization.

Memory Built-In Self-Test Requirements.

Overview of Memory BIST Requirements. At-Speed Operation.

An Example Memory BIST.

A Memory Built-In Self-Test. Optional Operations. An Example Memory Built-In Self-Test.

MBIST Chip Integration Issues.

Integrating Memory BIST.

MBIST Integration Concerns.

MBIST Default Operation.

MBIST Power Concerns.

Banked Operation.

MBIST Design-Using LFSRs.

Pseudo-Random Pattern Generation for Memory Testing. Signature Analysis and Memory Testing. Signature Analysis and Diagnostics.

Shift-Based Memory BIST.

Shift-Based Memory Testing. Output Assessment.


Purpose and Function of ROM BIST. The ROM BIST Algorithm. ROM MISR Selection. Signature Compare Method.

Memory Test Summary. Recommended Reading.

5. Embedded Core Test Fundamentals.

Introduction to Embedded Core Testing.

Purpose. Introduction to Embedded Core-Based Chip Testing. Reuse Cores. Chip Assembly Using Reuse Cores.

What Is a Core?

Defining Cores. The Core DFT and Test Problem. Built-In DFT.

What is Core-Based Design?

Design of a Core-Based Chip. Core-Based Design Fundamentals.

Reuse Core Deliverables.

Embedded Core Deliverables.

Core DFT Issues.

Embedded Core-Based Design Test Issues.

Development of a Reusable Core.

Embedded Core Considerations for DFT.

DFT Interface Considerations-Test Signals.

Embedded Core Interface Considerations for DFT-Test Signals.

Core DFT Interface Concerns-Test Access.

Test Access to the Core Interface.

DFT Interface Concerns-Test Wrappers.

The Test Wrapper as a Signal reduction Element. The Test Wrapper as a Frequency Interface. The Test Wrapper as a Virtual Test Socket.

The Registered Isolation Test Wrapper. The Slice Isolation Test Wrapper. The Isolation Test Wrapper-Slice Cell. The Isolation Test Wrapper-Core DFT Interface. Core Test Mode Default Values.

Internal versus External Test Quiescence Defaults Application.

DFT Interface Wrapper Concerns.

Lack of Bidirectional Signals. Test Clock Source Considerations.

DFT Interface Concerns-Test Frequency.

Embedded Core Interface Concerns for DFT-Test Frequency. Solving the Frequency Problem.

Core DFT Development.

Internal Parallel Scan. Wrapper Parallel Scan. Embedded Memory BIST. Other DFT Features.

Core Test Economics.

Core DFT, Vectors, and Test Economics. Core Selection with Consideration to DFT Economics.

Chip Design with a Core.

Elements of a Core-Based Chip. Embedded Core Integration Concerns. Chip-Level DFT.

Scan Testing the Isolated Core. Scan Testing the Non-Core Logic.

Scan Testing the Non-Core Logic in Isolation. Chip-Level Testing and Tester Edge Sets.

User Defined Logic Chip-Level DFT Concerns. Memory Testing with BIST. Chip-Level DFT Integration Requirements.

Embedded Core-Based DFT Integration Architecture. Physical Concerns.

Embedded Test Programs. Selecting or Receiving a Core. Embedded Core DFT Summary. Recommended Reading.

About the CD.

Glossary of Term.


About the Author.



This book is made primarily for design engineers and managers, and for test and design-for-test engineers and managers. It can also be used for students of digital design and test, as well. The purpose of this book is to introduce the basic concepts of test and design-for-test (DFT), and to then address the application of these concepts with an eye toward the trade-offs of the engineering budgets (silicon area, operating frequency target, power consumption, etc.), the business drivers, and the cost factors.

Currently, some very good test and DFT texts are available. However, many of them are from an academic focus. In my years of being part of the integrated circuit design community, I have had to train many IC designers and junior DFT engineers in test and design-for-test. I have discovered that corporate education is remarkably different from academic education. A design engineer on a project, who must learn and apply DFT techniques, is learning them while being responsible for 60+ hours of other design tasks per week and while meeting regular design deadlines and milestones. In this environment, learning the DFT tasks and techniques is difficult with a book that focuses on the "mathematical" or "theoretical" point of view. History has taught me that a direct "how to do it" text is more effective.

Another interesting aspect of the competitive corporate environment is that the design process may be "factory-ized." The overall design process for a chip or a portion of a chip is no longer the responsibility of the design engineer, but of teams of chip design functions. For example, the logic gate cells may be designed and characterized by one group (standard cell and library development), and the design may be modeled and synthesized by a different group (HDL design and synthesis), verified by yet another group (formal and simulation verification), and ultimately, mapped to a physical process by yet another group (floorplanning, place&route, and physical design). In this case, the teaching of DFT techniques must be spread out to the various organizations contributing to the overall design. A teaching description of a DFT technique, such as scan design, is not effective if it is not related to the tasks, scheduling, trade-offs, and the separations into the various organizational elements. Again, history and experience have taught me that an effective text here is one that relates the topic being addressed to the design methodology and design flow.

So direct experience in corporate technical training and teaching has led to the style and content of this "practical guide" on the test and Design-for-Test (DFT) topics of scan test, embedded memory test, and embedded core test. This text has been developed more along the lines of a "just what you need to know—and how to do it" guide that explains the topic, explains the trade-offs, and relates the topic to the design flow. My hope is that using this text will reduce the "learning curve" involved in the application of test and design-for-test techniques, and will result in designs that have a higher quality-reliability level and a lower cost-of-test.

A practical text on DFT and DFT techniques, based on the industry point of view, is needed right now for several reasons. First, the "cost of test" is beginning to dominate the recurring (per-part) cost involved in the manufacturing of the final silicon product for many of the consumer markets—parts with high volume and a low selling price. Second, shorter product lifetimes and increased time-to-market (TTM) and time-to-volume (TTV) pressures are forcing the need to have some form of structured, repeatable and automatable test features included in the device as part of the overall design methodology. Third, the move to reuse cores, and core-based design, as a reaction to shrinking process geometries and TTM pressures, is also forcing designed-in test features to become portable since design units may be distributed and reused in several different chip designs with completely different configurations. And finally, the shrinking process geometries also enable "system-on-a-chip" and ULSI (Ultra-Large Scale Integrated) designs with massive integration—more integration means more faults and more vectors—which leads to a test data management and cost-of-test problems.

Taken all together, these changes in parts of the semiconductor design industry are changing the way test and DFT are viewed, addressed, and implemented. Organizations that once ignored DFT are now being dragged kicking and screaming into modern age because of test cost, TTM, TTV, test data volume, and having to deal with the test features delivered with commercially available cores. Test is one of the three major components of recurring per-part cost involved with the manufacture and selling of digital semiconductor integrated circuits (with the cost of silicon die and the cost of packaging being the other two). As with every product, trade-offs are made to achieve a quality level and to fit within a target cost profile. I hope that this text will eliminate the view that understanding the cost-of-test and applying DFT during the design phase of a product is a "black art" for organizations and individuals that must address managing the cost factors of a chip design.

If you have questions or comments, I can be contacted at Al_Crouch@prodigy.net


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