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CMOS/BiCMOS ULSI: Low Voltage, Low Power

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CMOS/BiCMOS ULSI: Low Voltage, Low Power

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Features

  • Comprehensive coverage of low-voltage, low-power digital VLSI design—Including process integration, device modeling and characterization, as well as techniques and concepts for digital circuits and subsystems design in a low-voltage, low-power environment.
    • Allows students to understand the importance of low-power design and how it affects the portability, reliability, cost, and environment in VLSI and GSI engineering. Ex.___

  • Latest developments in CMOS/BiCMOS VLSI design—With an in-depth analyses on the fabrication technologies for realization of low-voltage, low-power CMOS/BiCMOS structures.
    • Presents the most up-to-date information as it relates to future trends and directions of the CMOS/BiCMOS processes as well as portable communications. Ex.___

  • Latest BJT models—Such as HICUM, METRAM, and VBIC and MOS models such as EKV and BSIM4.
    • Presents a comprehensive overview of current available models. Ex.___

  • Integration of SOI technology and the latest copper metallization scheme—With CMOS/BiCMOS technology ultra high-speed applications.
    • Demonstrates the value and uses of the latest technological advances. Ex.___

Description

  • Copyright 2002
  • Edition: 1st
  • Book
  • ISBN-10: 0-13-032162-1
  • ISBN-13: 978-0-13-032162-6

The complete guide to CMOS/BiCMOS ULSI and GSI for every circuit design professional.

  • The in-depth, up-to-the-minute guide to low-power, low-voltage circuit design
  • Process integration, device modeling, and characterization
  • Includes the latest MOS and bipolar models
  • Advanced copper metallization techniques, deep submicron processes, and isolation techniques

Today's engineers must build devices that are more portable, more reliable, and more cost-effective than ever before. To this end, power has become a crucial consideration in ultra-large-scale-integration (ULSI) and giga-scale integration (GSI) engineering. BiCMOS technology now represents the optimal solution for a wide range of advanced applications. In this book, three of the field's leaders present in-depth coverage of the latest developments in CMOS/BiCMOS ULSI design—including thorough analyses of the fabrication technologies needed to realize low-voltage, low-power CMOS/BiCMOS structures.

Unlike previous books, CMOS/BICMOS ULSI covers low-voltage, low-power circuit design from all perspectives, including process integration, device modeling, and characterization. Coverage includes:

  • MOS/BiCMOS process technology and integration, including manufacturing considerations, advanced isolation techniques, and breakthrough copper metallization schemes
  • Device behavior and modeling, including new bipolar models such as HICUM, MEXTRAM, and VBIC, and key MOS models such as EKV, BSIM, and Philips MOS9 Model
  • In-depth comparisons of circuit techniques, configurations, and features of single battery operation
  • Altering transistor positions: New techniques for designing low-voltage, low-power latches and flip-flops

BiCMOS combines the low-power dissipation and high packing density of CMOS with the high speed and high output drive of bipolar devices. Using this book's state-of-the-art design techniques, you can leverage BiCMOS to its fullest advantage.

Sample Content

Online Sample Chapter

Low-Power Design: An Overview

Table of Contents

(NOTE: Each chapter begins with an Introduction and concludes with References.).

Acknowledgments.


Nomenclature.


Preface.


1. Introduction.

Low-Power Design: An Overview. Low-Voltage, Low-Power Design Limitations. Silicon-On-Insulator (SOI). From Devices to Circuits.



2. MOS/BiCMOS Process Technology and Integration.

The Realization of BiCMOS Processes. BiCMOS Manufacturing and Integration Considerations. Isolation in BiCMOS. Integrated Analog/Digital BiCMOS Process. Deep Submicron Processes. Low-Voltage/Low-Power CMOS/BiCMOS Processes. Future Trends and Directions of CMOS/BiCMOS Processes. Conclusions.



3. Device Behavior and Modeling.

The MOS(FET) Transistor. The Bipolar (Junction) Transistor. The Bipolar (Junction) Transistor. MOSFET SPICE Models. Advanced MOSFET Models. Advanced MOSFET Models. Bipolar SPICE Models. Bipolar SPICE Models. Bipolar SPICE Models. The MOSFET in a Hybrid-Mode Environment. Summary.



4. Low-Voltage, Low-Power Logic Circuits.

Conventional CMOS Logic Gates. Conventional BiCMOS Logic Gate. BiCMOS Circuits Utilizing Lateral pnp BJTs in pMOS Structures. Merged BiCMOS Digital Circuits. Full-Swing Multidrain/Multicollector Complementary BiCMOS Buffers. Quasi-Complementary BiCMOS Digital Circuits. Full-Swing BiCMOS/BiNMOS Digital Circuits Employing Schottky Diodes. Feedback-Type BiCMOS Digital Circuits. High-Beta BiCMOS Digital Circuits. Transiently Saturated Full-Swing BiCMOS Digital Circuits. Transiently Saturated Full-Swing BiCMOS Digital Circuits. Bootstrapped-Type BiCMOS Digital Circuits. ESD-Free BiCMOS Digital Circuit. Conclusion.



5. Low-Power Latches and Flip-Flops.

Evolution of Latches and Flip-Flops. Quality Measures for Latches and Flip-Flops. Latches and Flip-Flops: A Design Perspective.



A. Basic Equations.

Current Equations. Charge Equations. Noise Equations. Parameter Scaling (Geometrical scaling and temperature scaling).



B. Model Equations.

DC Current Model. Charge Model. Noise Model.



C. Hyperbolic (HYP) Functions.


D. JUNCAP Model.

Temperature, Geometry, and Voltage Dependence. JUNCAPCapacitor and Leakage Current Model.



Index.


About the Authors.

Preface

Preface

With advances in ultra-large-scale-integration (ULSI) technology, the industry is now on the brink of logic integrated circuits (ICs) packed with over 100 million transistors, whose device feature dimensions are far smaller than the wavelength of visible light. This trend, together with the never-ending demand for maximum speed and minimum power, has shaped a new arena in which the Complementary Metal Oxide Semiconductor (CMOS) and Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) technologies have found themselves gaining importance and attracting keen interest in digital, analog, and even radio-frequency IC design. This development has led many business leaders and market visionaries to predict that the best is yet to come, and the established trend will stay with us for a long time.

This book begins with an introductory chapter on the history of semiconductor devices and its evolution throughout the years. It also addresses the importance of low power design and how it affects the portability, reliability, cost, and even environment in very-large-scale-integration (VLSI) and giga-scale-integration (GSI) engineering. A thorough review of low-voltage, low-power design limitations in relation to the power supply voltage, threshold voltage, scaling, and interconnect wires is detailed. Chapter 1 concludes with the challenges facing future device and circuit designers, caused by the ongoing shrinking of device dimensions and the never-ending growing complexities of integrated circuits.

Upon introducing the basics of BiCMOS devices, chapter 2 moves on to describe the different key BiCMOS process technologies as well as discuss the design considerations for achieving high-performance BiCMOS devices. A review of various isolation technologies, new planarization methods for shallow trench isolation (STI) structures, and the latchup phenomenon are detailed in this chapter. A new characterization method for the 0.18-mm ultra-shallow STI CoSi2 CMOS test structures is also reported. Deep submicron processes such as that for the realization of polysilicon emitter BiCMOS structure, low-capacitance bipolar/BiCMOS devices, silicon-on-insulator (SOI) CMOS/BiCMOS VLSI, copper interconnects for deep submicron SOI CMOS/BiCMOS structures, and low-voltage, low-power CMOS/BiCMOS structures are also described in great depth. Finally, the chapter finishes with a discussion of the future trends and directions of the CMOS/BiCMOS processes.

In chapter 3, the fundamentals of both MOSFETs and bipolar junction transistors (BJTs) are provided before moving on to describing the main models of the MOS and BJT. The assumptions made while developing these models together with the models' performance in technologically scaled environment are highlighted and explained in detail. A separate section is devoted to the analytical and experimental characterization of the sub-half micron-MOS devices, the modeling of lateral pnp BJTs in the pMOSFET structures, and the trends and general features of the various device/process parameters of scaled pMOSFETs operating in a hybrid-mode environment. A methodology to construct a device model for a given wafer, using device characterization tools based on the successful retrieval of experimental data, is presented toward the last part of this chapter. The chapter ends with a summary of all models reviewed, which are the MOSFET SPICE models such as the LEVEL1, LEVEL2, and LEVEL3 models; BSIM1, BSIM2, and BSIM3 models; HSPICE Level 50 (Philip MOS9) model; EKV MOSFET model; bipolar SPICE models; Ebers-Moll model; Gummel-Poon model; modified Gummel-Poon model; MEXTRAM model; HICUM; and VBIC model.

Chapter 4 presents an in-depth analysis and the development of a new generation of CMOS/BiCMOS circuits for present and future VLSI and GSI requirements. Different circuit design concepts, ideas, and techniques are explained in detail to show how they are implemented to enhance the circuit performance (speed and/or power) or to balance these conflicting constraints to achieve a required specification. In ultra-low-voltage design, the output voltage swing of a logic gate cannot be compromised. Hence, in this chapter, much attention is devoted to full-swing CMOS/BiCMOS circuits and the inherent techniques such as bootstrapping and transient saturation. The merged BiCMOS, the multidrain/multicollector complementary BiCMOS, the quasi-complementary BiCMOS, the feedback BiCMOS, the Schottky BiCMOS/BiNMOS, the high-b BiCMOS, the transiently saturated BiCMOS, and the bootstrapping CMOS/BiCMOS circuits are also covered in depth. A comparative evaluation of the various CMOS/BiCMOS circuits and how they are being applied in a low-voltage, low-power environment is presented.

Even though chapter 4 covers a wide range of logic gates pertaining to low-voltage, low-power IC design, it is important to step up from the basic cell design to the circuit design. In that respect, latches and flop-flops, which are commonly found in synchronous and asynchronous systems, are described in chapter 5. This chapter starts with an introductory section to explain the need for low-power latches and flip-flops. It also profiles the basics of latches and flip-flops-their functionality, types, applications, design styles, and development through the years. Because latches and flip-flops are used to store logic values, the traditional measures of area, speed, and power dissipation are not exhaustive and are insufficient to access their quality. Hence, it becomes imperative to have a comprehensive set of quality measures to evaluate all aspects of a design decision. The quality measures described in this chapter are composed of four main measures-performance, power dissipation, area, and sensitivity to voltage/technology scaling. Finally, the chapter concludes with the various design styles such as dynamic, static, and semistatic used in single edge-triggered flip-flops, and double edge-triggered flip-flops.

In conclusion, this book provides an in-depth insight into the low-power design aspects of CMOS/BiCMOS technology, together with the most recent advances in the area. The information presented shall be extremely beneficial and valuable to students, instructors, circuit designers, engineers, scientists, and professors who are already working or about to embark in this very important field of portable integrated electronics.

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