Basic Concepts for Semiconductor Power Delivery
Power delivery is a major challenge in present-day systems. This challenge is expected to increase in the next decade as systems become smaller and new materials are introduced into packages and boards. As devices scale and more transistors are integrated into a single integrated circuit, the power and current levels are expected to increase with a corresponding decrease in the voltage. With gigabit signals being propagated through the package and board, the ability to supply clean power to the transistor circuits becomes very critical. In addition, electromagnetic interference levels have to be kept low in the system to manage coupling and crosstalk.
In this chapter, the basics of power delivery are described. Along with a description of the components of a power delivery network (PDN), the analysis methodology of such networks is described with examples.
1.1.1 Functioning of Transistors
Integrated circuits (ICs) such as microprocessors, field programmable gate arrays, memory devices, and other application-specific ICs contain transistors. Transistors are multiterminal switches that can be turned on or off on the basis of a control signal. The on or off position of the switch determines the current flowing through the device. In complementary metal oxide semiconductor (CMOS) field effect transistor (MOSFET) technology (which is the most popular technology used to design microprocessors), two types of transistors are used, namely the NMOS (n-channel) transistor and the PMOS (p-channel) transistor. The detailed operation of these devices can be obtained from . In this book, for simplicity, we will assume that both transistors are three-terminal devices that can be represented using switches, as shown in Figure 1-1. The three terminals are called the gate, source, and drain. By applying a voltage between the gate and source, the current through the transistor (from drain to source for NMOS and reverse for PMOS) can be turned on or off. The NMOS transistor is called as a normally open switch, since a gate voltage has to be applied to pass current through the transistor. Hence, if a binary 0 (logic level low) signal exists at the gate, the switch is OFF, and when a binary 1 (logic level high) signal is available at the gate, the switch turns ON. The reverse is true for the PMOS transistor, since a binary 1 level at the gate turns OFF the current, while a binary 0 level at the gate allows current to pass, that is, the switch is ON. Hence, the PMOS transistor is called as the normally closed switch. The drain and gate terminals of the NMOS and PMOS transistors can be connected together to form an inverter, which is one of the basic building blocks in any IC. We limit ourselves to the discussion of such an inverter in this section.
Figure 1-1 NMOS and PMOS transistors represented as switches.
Figure 1-2 shows the inverter circuit. The gate connection is called as the input node, and the drain connection is called as the output node. The output node is connected to the input node of the following transistor circuit. Since the gate of the transistors acts as a capacitor (formed between the metal-oxide-semiconducting substrate), the inverter (also called the driver) is used to charge and discharge the input capacitance of the succeeding stage. The capacitor must be charged to reach the binary 1 voltage level. Similarly, discharging a capacitor to 0 voltage requires the removal of charge. The inverter circuit must be connected to a power supply (shown as Vdd and Gnd terminals), which provides the ability to charge and discharge a capacitor node within the IC. In Figure 1-2, a wire (interconnection) is used between the two inverters to act as a conduit for the charge, and Ron is the on resistance of the transistor. The speed at which the circuit operates determines how quickly charge can be either supplied or removed from the capacitor through the switches. A PDN in a system provides the interconnection framework to make this happen, supplying the transistors with sufficient voltage and current for them to switch states.
Figure 1-2 (a) Driver (inverter) connected to a receiver (inverter). (b) Input capacitance of receiver being charged to Vdd.
1.1.2 What Are the Problems with Power Delivery?
The power supply (which is the source of the voltage and current) is typically bulky and cannot be connected directly to the Vdd and Gnd terminals of the IC. Therefore, wires (interconnections), which have resistance and inductance in them, are used to establish this connection. The current flowing through these wires creates both a DC drop (not shown) and time-varying fluctuation of the voltage across the Vdd and Gnd terminals of the IC (shown in Figure 1-3), which is detrimental to the transistors in the IC. Hence, a suitable PDN must be created between the power supply and the IC, such that the voltage is well regulated for the required current to be supplied to the transistors over a required time period. The voltage fluctuation across the Vdd and Gnd terminals of the transistors can cause the following problems with the transistors:
- Reduction in voltage across the power supply terminals of the IC that slows down the transistor or prevents the transistor from switching states.
- Increase in voltage across the power supply terminals of the IC, which creates reliability problems.
- Leakage of the voltage fluctuation into a quiet transistor, as shown in Figure 1-3, causing incorrect switching of quiet transistor circuits at the far end of a communication path along with crosstalk from neighboring signal lines.
- Timing margin errors caused by degraded waveforms at the output of the drivers.
The voltage fluctuation across the power supply of the IC is called power supply noise, delta I noise, or simultaneous switching noise (SSN), since it occurs only during the switching of the transistors.
1.1.3 Importance of Power Delivery in Microprocessors and ICs
Given the voltage fluctuations across the power supply of a transistor, it is helpful to understand how a microprocessor operates (as an example at a holistic level) and the impact of voltage fluctuations on microprocessor performance.
A microprocessor consists of millions of CMOS transistors interconnected through wires in a very complex fashion. The microprocessor speed can be limited by the gate (or transistor) delays, interconnect (or wire) delays, or both. The inverse of the gate delay (frequency) is proportional to the gate voltage. For a gate-dominated circuit, a 1% drop in the gate voltage results in nearly a 1% drop in frequency. The interconnect delay, however, is a very weak function of voltage. An important relationship exists between the operating voltage of the microprocessor and its speed (measured as frequency) around the nominal voltage of the microprocessor. This relationship is shown in Figure 1-4 for a 64-bit Scalable Processor Architecture (SPARC) microprocessor . Around the nominal voltage of 1.6 V, the relationship between frequency and voltage is almost linear. As the graph shows, a reduction in voltage reduces the operating frequency of the microprocessor, while an increase in voltage increases its frequency. This important relationship is true in most microprocessors, and we use this example to explain the impact of power supply fluctuations on the operating frequency of the microprocessor. In reality, the relationship between processor performance and voltage is more complex and depends not only on the magnitude of power supply noise but also on the frequency of the noise.
Figure 1-4 Frequency-voltage relationship for the 64-bit SPARC V9 microprocessor. The chip is built using a 150-nm technology that has seven layers of aluminum interconnects. It is designed to operate at 1.0 GHz with a supply voltage of 1.6 V. The temperature is maintained at 60°C .
Consider Figure 1-5, which assumes a linear relationship between the frequency of a microprocessor (along the y-axis) and voltage (along the x-axis), as in Figure 1-4. In Figure 1-5, FMAX is the maximum operating frequency of the microprocessor. Any voltage above 1.65 V causes reliability problems and is shown as the reliability wall. Any voltage that falls within the reliability wall causes the dielectric breakdown of the gate oxide in the MOSFET due to excessive electric field. Hence, the power supply voltage cannot exceed 1.65 V for this example. Let's assume initially that the operating voltage of the microprocessor is 1.55 V. According to the graph, the nominal FMAX for the microprocessor is 720 MHz. However, voltage variations on the power supply cause the voltage to vary plus or minus 100 mV around the nominal voltage. On the high side, a voltage of 1.65 V (1.55 V + 100 mV) is below the maximum allowed voltage of 1.65 V, which ensures no reliability problems. On the low side, the power supply voltage reduces to 1.45 V (1.55 V - 100 mV). At 1.45 V, FMAX now becomes 670 MHz. Hence, any drop or reduction in the power supply voltage causes the microprocessor to operate at a lower frequency. In other words, the PDN causing the variations on the power supply terminals of the IC results in the slowdown of the microprocessor. Similarly, a voltage rise across the power supply of the IC, if it exceeds the maximum voltage allowable, causes the IC to malfunction.
In the design of PDNs, the focus is always on minimizing the voltage droop on the power supply terminals of the transistor circuits within an IC and also on ensuring that the voltage maximum does not cause reliability problems .
1.1.4 Power Delivery Network
A PDN consists of a power supply, DC–DC converters (also called voltage regulator modules, or VRMs), lots of decoupling capacitors, and interconnections that act as conduits for the supply and removal of charge to and from the switching circuits. In a typical computer system, the IC is packaged and placed on a motherboard (with or without a socket) with a power supply on the motherboard. The power supply provides high voltage and current to the motherboard. The voltage is reduced through a DC–DC converter and supplied to the IC through the interconnections in the motherboard and package. The decoupling capacitors are distributed on the motherboard, package, and IC; they act as reservoirs where charge can be stored. The charge is supplied as needed to the transistors from the decoupling capacitors. The proximity of the capacitors to the switching circuits determines the time required to supply the charge. The required time is controlled by the speed of light in the medium, which is the minimum time required to transfer the charge from the capacitor to the transistors. As an example, the minimum time required to supply charge from a capacitor placed on the motherboard 6 inches away from a transistor circuit is 1 ns, since the speed of light in typical printed circuit boards (PCBs) is 166 ps/inch.
A typical PDN for a semiconductor is shown in Figure 1-6 . Since the inverse of time delay is frequency, the proximity of the capacitors to the transistors determines if the capacitor supplies charge at high frequencies, middle frequencies, or low frequencies. The high-, mid-, and low-frequency capacitors are shown in the figure, where a capacitor farther away from the IC is always large and bulky, thereby operating at a lower frequency. The charge storage capacity of the large capacitors is of the order of thousands of microfarads, much higher than either the high- or mid-frequency capacitors, which are in the nanofarad range.
Figure 1-6 Power delivery network. By permission from D. Herrell and B. Beker, “Modeling of power distribution systems in PCs,” in Proceedings of the EPEP ’98 Conference, pp. 159-162, © 1998 IEEE.
1.1.5 Transients on the Power Supply
Although the operating frequency of a microprocessor can be high (1 GHz and higher), power supply fluctuations can be caused over a range of frequencies, because a computer is a broadband system in which transistors switch at multiple frequencies. For example, a 1 GHz microprocessor in a system may be executing instruction at 1 GHz, causing voltage fluctuations at the 1 GHz frequency. At the same time, the microprocessor may be writing data to the cache on the PCB at 400 MHz and operating the Joint Test Access Group (JTAG) line for testing the hardware at 1 MHz. Such a switching activity can cause voltage fluctuations over a range of frequencies, which makes the design of the PDN very difficult. Voltage variation on the power supply at multiple frequencies is shown in Figure 1-7 for a microprocessor . For an IC, the transient current flowing through an inductor, L in Figure 1-3, causes voltage drop, VL, across it, given by
Figure 1-7 Noise signature. By permission from A. Muhtaroglu, G. Taylor, and T. Rahal-Arabi, “On-die droop detector for analog sensing of power supply noise,” IEEE Journal of Solid-State Circuit, vol. 39, no. 4, pp. 651–660, Apr. 2004, © 2004 IEEE.
where dI/dt is the rate of change of current in the circuit. The inductor L can be equal to LV or LG, or a combination of the two depending on the current path. A positive dI/dt through the inductor causes a voltage drop across it, resulting in a reduction in the supply voltage across the IC terminals and causing a performance problem due to a negative spike in the IC supply voltage. Similarly, a negative dI/dt through the inductors increases the supply voltage across the IC terminals, resulting in a positive spike, which causes reliability problems. The power supply noise has four components (1) ultra-high-frequency noise in the 10 to 100 GHz range, (2) high-frequency noise in the 100 to 1000 MHz range, (3) mid-frequency noise in the 1 to 10 MHz range, and (4) low-frequency noise in the 1 to 100 KHz range. The inductance on-chip affects both the ultra-high- and high-frequency noise (>1 GHz), while the package has a large effect on the high-frequency and mid-frequency noise components (10 MHz-1 GHz). The inductance of the motherboard and the voltage regulator module affect the mid-frequency and low-frequency noise components (<1 MHz), as shown in Figure 1-7.
The ultra-high-, high-, mid-, and low-frequency noise are also called, respectively, the first, second, third, and fourth droops or spikes on the power supply.