This is the definitive reference for the latest generation of the enormously popular and influential SPARC microprocessors — the 64-bit SPARC-V9 — which is now being used by a variety of computer system vendors and is destined to set the standard for high performance capacity into the next century. KEY TOPICS: Describes the architecture and instruction set of the 64-bit SPARC-V9 — a RISC-style processor architecture that supports a linear address space accessed by 64-bit addresses, fault-tolerance, object-oriented software, lightweight threads, and superscalar and multiprocessor implementations. MARKETS: For implementors of the SPARC architecture, microprocessor designers, hardware engineers, developers of SPARC-V9 system software, software engineers who write SPARC-V9 software in assembly language; and for students of computer architecture.
3. Architectural Overview.
4. Data Formats.
8. Memory Models.
Annex A: (Normative) Instruction Definitions.
Annex B: (Normative) IEEE 754-1985 Requirements for SPARC-V9.
Annex C: (Normative) SPARC-V9 Implementation Dependencies.
Annex D: (Normative) Formal Specification of the Memory Models.
Annex E: (Informative) Opcode Maps.
Annex F: (Informative) SPARC-V9 MMU Requirements.
Annex G: (Informative) Suggested Assembly Language Syntax.
Annex H: (Informative) Software Considerations.
Annex I: (Informative) Extending the SPARC-V9 Architecture.
Annex J: (Informative) Programming With the Memory Models.
Annex K: (Informative) Changes from SPARC-V8 to SPARC-V9.