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Real World FPGA Design with Verilog

Real World FPGA Design with Verilog

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  • Copyright 2000
  • Dimensions: 7 X 9-1/4
  • Pages: 291
  • Edition: 1st
  • eBook (Adobe DRM)
  • ISBN-10: 0-13-244142-X
  • ISBN-13: 978-0-13-244142-1

The practical guide for every circuit designer creating FPGA designs with Verilog!

Walk through design step-by-step-from coding through silicon. Partitioning, synthesis, simulation, test benches, combinatorial and sequential designs, and more.

Real World FPGA Design with Verilog guides you through every key challenge associated with designing FPGAs and ASICs using Verilog, one of the world's leading hardware design languages. You'll find irreverent, yet rigorous coverage of what it really takes to translate HDL code into hardware-and how to avoid the pitfalls that can occur along the way. Ken Coffman presents no-frills, real-world design techniques that can improve the stability and reliability of virtually any design. Start by walking a typical Verilog design all the way through to silicon; then, review basic Verilog syntax, design; simulation and testing, advanced simulation, and more. Coverage includes:

  • Essential digital design strategies: recognizing the underlying analog building blocks used to create digital primitives; implementing logic with LUTs; clocking strategies, logic minimization, and more
  • Key engineering tradeoffs, including operating speed vs. latency
  • Combinatorial and sequential designs
  • Verilog test fixtures: compiler directives and automated testing
  • A detailed comparison of alternative architectures and software-including a never-before-published FPGA technology selection checklist

Real World FPGA Design with Verilog introduces libraries and reusable modules, points out opportunities to reuse your own code, and helps you decide when to purchase existing IP designs instead of building from scratch. Essential rules for designing with ASIC conversion in mind are presented.

If you're involved with digital hardware design with Verilog, Ken Coffman is a welcome voice of experience-showing you the shortcuts, helping you over the rough spots, and helping you achieve competence faster than you ever expected!

Sample Content

Table of Contents

1. Verilog Design in the Real World.

Trivial Overheat Detector Example. Synthesizable Verilog Elements. Verilog Hierarchy. Built-In Logic Primitives. Latches and Flipflops. Blocking and Nonblocking Assignments. Miscellaneous Verilog Syntax Items.

2. Digital Design Strategies and Techniques.

Design Processing Steps. Analog Building Blocks for Digital Primitives. Using a LUT to Implement Logic Functions. Discussion of Design Processing Steps. Synchronous Logic Rules. Clocking Strategies. Logic Minimization. What Does the Synthesizer Do? Area/Delay Optimization.

3. A Digital Circuit Toolbox.

Verilog Hierarchy Revisited. Tristate Signals and Busses. Bidirectional Busses. Priority Encoders. Area/Speed Optimization in Synthesis. Trade-off Between Operating Speed and Latency. Delays in FPGA Logic Elements. State Machines. Adders. Subtractors. Multipliers.

4. More Digital Circuits: Counters, RAMs, and FIFOs.

Ripple Counters. Johnson Counters. Linear Feedback Shift Registers. Cyclic Redundancy Checksums. ROM. RAM. FIFO Notes.

5. Verilog Test Fixtures.

Compiler Directives. Automated Testing.

6. Real World Design: Tools, Techniques, and Trade-offs.

Compiling with LeonardoSpectrum. Complete Design Flow, 8-Bit Equality Comparator. 8-Bit Equality Comparator with Hierarchy. Optimization Options In the Xilinx Environment. Mapping Options. Logic Level Timing Report/Post Layout Timing Report. VHDL/Verilog Simulation Options. Other Design Manager Tools.

7. A Look at Competing Architectures.

Factors that Determine Integrated Circuit Pricing. FPGA Device Design. FPGA Technology Selection Checklist. Xilinx FPGA Architectures. Altera CPLD Architectures.

8. Libraries, Reusable Modules, and IP.

Keys to Increased Productivity. Library Elements. Structural Coding Style. A Small Diversion to Compare a Schematic to a Verilog Design. Using LogiBLOX Module Generator. Design Reuse, Reusing Your Own Code. Buying IP Designs. Summing Up.

9. Designing for ASIC Conversion.

HardWire Devices. Semicustom Devices. Design Rules for ASIC Conversion. Synchronous Design Rules. Oscillators. Delay Lines. The Language of Test. Print-on-Change Test Vectors. Afterword-A Look into the Future. Resources. Glossary and Acronyms. Bibliography.


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