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FireWire System Architecture: IEEE 1394A, 2nd Edition
- By MindShare, Inc., Don Anderson
- Published Dec 17, 1998 by Addison-Wesley Professional.
Book
- Sorry, this book is no longer in print.
Description
- Copyright 1999
- Dimensions: 7-3/8" x 9-1/4"
- Pages: 544
- Edition: 2nd
- Book
- ISBN-10: 0-201-48535-4
- ISBN-13: 978-0-201-48535-6
Praise for the first edition:
"Finally, a book on IEEE 1394 that's easy to understand!!! MindShare's FireWire System Architecture: IEEE 1394 provides a consolidated learning tool for 1394 hardware and software, and confirms the statement, '1394's for the fun stuff....'"
-Phil Roden, 1394 Digital Design Manager, Texas Instruments
The FireWire (IEEE 1394a) standard for high-speed serial bus communications has come to the fore as an important technology supporting today's emerging data-intensive applications.
FireWire System Architecture provides an in-depth description of the IEEE 1394a cable environment, based on the 2.0 version of the 1394a standard. Comprehensive, concise, and well-organized, this book details the specification itself and presents the architecture, features, and operations of systems developed with the FireWire bus. Completely up-to-date, this new edition covers all of the changes incorporated into the 2.0 standard, such as arbitration enhancements, improvements in bus reset timing, new PHY register definition, and port interface enhancements to support suspend/resume and port disable. In addition, it provides in-depth information on suspend/resume operation, power distribution, and power management.
FireWire System Architecture describes the various hardware and software layers that make up the FireWire serial bus and provides transaction examples to explain and illustrate the relationship between each layer.
It explores such essential topics as:
- The communications model
- Asynchronous and isochronous transactions
- Cables and connectors
- The electrical interface
- Asynchronous and isochronous arbitration, including such enhancements as fly-by arbitration, acceleration control, and priority arbitration service
- Packets, including the PHY packet format
- Serial bus configuration and management
- Control and status registers (CSRs)
- Configuration ROM
- Power management
Numerous sample implementations throughout the book demonstrates how theory is put to use in real-world applications. This combination of comprehensive reference, readable explanation, and examples make this guide indispensable for anyone who works with the IEEE 1394a technology.
The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title is designed to illustrate the relationship between the software and hardware, and thoroughly explains the architecture, features, and operation of systems built using one particular type of chip or hardware specification.
Sample Content
Table of Contents
(Most chapters begin with an Overview.)
About This Book.
The MindShare Architecture Series
Cautionary Note.
Organization of This Book.
Part One: Introduction to FireWire (IEEE 1394).
Part Two: Serial Bus Communications.
Part Three: Serial Bus Configuration.
Part Four: Serial Bus Management.
Part Five: Registers and Configuration ROM.
Part Six: Power Management.
Appendix.
Target Audience.
Prerequisite Knowledge.
Documentation Conventions.
Labels for Multi-byte Blocks.
Hexadecimal Notation.
Binary Notation.
Decimal Notation.
Bit Versus Byte Notation.
Identification of Bit Fields (logical groups of bits or signals).
Visit Our Web Page.
We Want Your Feedback.
I. INTRODUCTION TO FIREWIRE (IEEE 1394a).
1. Why FireWire?Motivations Behind FireWire Development.
Inexpensive Alternate to Parallel Buses.
Plug and Play Support.
Eliminate Host Processor/Memory Bottleneck.
High Speed Bus with Scalable Performance.
Support for Isochronous Applications.
BackPlane and Cable Environments.
Bus Bridge.
1394 Applications.
IEEE 1394 Refinements.
Primary Features.
2. Overview of the IEEE 1394 Architecture.IEEE 1394 Overview.
Specifications and Related Documents.
IEEE 1394-1995 and the IEEE 1394a Supplement.
IEEE 1394.B.
Unit Architecture Specifications.
IEEE 1394 Topology.
Multiport Nodes and Repeaters.
Configuration.
Peer-To-Peer Transfers.
Device Bay.
The ISO/IEC 13213 Specification.
Node Architecture.
Address Space.
Transfers and Transactions.
Control and Status Registers (CSRs).
Configuration ROM.
Message Broadcast.
Interrupt Broadcast.
Automatic Configuration.
II. SERIAL BUS COMMUNICATIONS.
3. Communications Model.Transfer Types.
Asynchronous.
Isochronous.
The Protocol Layers.
Bus Management Layer.
Transaction Layer.
Link Layer.
Physical Layer.
A Sample Asynchronous Transaction.
The Request.
The Response.
An Example Isochronous Transaction.
4. Communications Services.Anatomy of Asynchronous Transactions.
The Request Subaction.
Response Subaction.
Anatomy of Isochronous Transactions.
Setting Up Isochronous Transactions.
Maintaining Synchronization.
Isochronous Transactions.
Isochronous Transaction Initiation & Reception.
5. Cables & Connectors.Cable and Connector Types.
6-pin Connector (1394-1995).
Make First/Break Last Power Pins.
Optional 4-pin Connector (1394a supplement).
Positive Retention.
Cable Characteristics.
6-Conductor Cables.
4-Conductor Cables.
Device Bay.
6. The Electrical Interface.Common Mode Signaling.
Differential Signaling.
Recognition of Device Attachment and Detachment.
IEEE 1394-1995 Device Attachment/Detachment.
IEEE 1394a Device Attachment/Detachment.
Bus Idle State.
The Port Interface.
Differential Signal Specifications.
Arbitration Signaling.
Line State Signaling (1, 0, and Z).
Line State Detection.
Reset Signaling.
Line States During Configuration.
Line States During Normal Arbitration.
Starting and Ending Packet Transmission.
Dribble Bits.
Port State Control.
Speed Signaling.
High Speed Devices Slowed Due to Topology.
Devices of Like Speed Directly Connected.
Speed Signaling Circuitry.
Data/Strobe Signaling.
NRZ Encoding.
Data-Strobe Encoding.
Gap Timing.
Cable Interface Timing Constants.
Suspend/Resume.
Cable Power.
Cable Power Requirements.
Power Class.
Power Distribution.
Bus Powered Nodes.
7. Arbitration.Arbitration Signaling.
Arbitration Services.
Asynchronous Arbitration.
Fairness Interval.
The Acknowledge Packet and Immediate Arbitration Service.
Isochronous Arbitration.
Cycle Start and Priority Arbitration.
Combined Isochronous and Asynchronous Arbitration.
Cycle Start Skew.
1394a Arbitration Enhancements.
Acknowledge Accelerated Arbitration.
Fly-by Arbitration.
Acceleration Control.
Priority Arbitration Service.
Summary of Arbitration Types.
8. Asynchronous Packets.Asynchronous Packets.
Data Size.
Write Packets.
Asynchronous Stream Packet.
Read Packets.
Lock Operations.
Lock Request Packet.
Lock Response Packet.
Response Codes.
Acknowledge Packet.
Asynchronous Transaction Summary.
Write Transactions.
Summary of Read and Lock Transactions.
Cycle Start Packet.
9. Isochronous Packet.Stream Data Packet.
Isochronous Data Packet Size.
Isochronous Transaction Summary.
10. PHY Packet Format.PHY Packet Format.
Self-ID Packets.
Self-ID Packet Zero.
Self-ID Packets One, Two, and Three (1394-1995).
Self-ID Packets One and Two (1394a).
Link-on Packet.
PHY Configuration Packet.
Force Root Node.
Gap Count Optimization.
Extended PHY Packets.
Ping Packet.
Remote Access Packet.
Remote Reply Packet.
Remote Command Packet.
Remote Confirmation Packet.
Resume Packet.
11. Link to PHY Interface.The Interface Signals.
Sharing the Interface.
PHY Initiated Transfers.
Link Initiated Transfers.
Determining Transfer Rate Between Link and PHY.
Powering the Link.
Packet Transmission.
Link Issues Request.
Receiving Packets.
PHY Reports Status.
ARB_RESET_GAP.
SUBACTION_GAP.
BUS_RESET_START.
PHY_INTERRUPT.
Accelerated Arbitration Control.
Accessing the PHY Registers.
PHY Register Reads.
PHY Register Writes.
Electrical Isolation Between PHY and Link.
12. Transaction Retry.Busy Retry.
The First Packet Transmission Attempt.
Single Phase Retry.
Dual Phase Retry.
Transactions Errors.
Packet Transmission Errors.
Packet Error Handling Summary.
III. SERIAL BUS CONFIGURATION.
13. Configuration Process.Bus Initialization (Bus Reset).
Tree Identification (The Family Tree).
Self Identification.
Bus Management.
14. Bus Reset (Initialization).Sources of Bus Reset.
Power Status Change.
Bus Reset Signaled by Attached Node.
Node Attachment or Removal.
MAX_ARB_STATE_TIME Expires.
Software Initiated Bus Reset.
Bus Reset Signaling.
Effects of Bus Reset.
Topology Information Cleared.
PHY Register Changes.
CSR Register Changes.
1394-1995 and Reset Runaway.
Problem One: The Reset Storm.
The 1394a Solution: Debounce Port Status Signal.
Problem Two: Recognition of Connection Change Not Symmetric.
The Solution: Slow Node Accepts Fast Node's Reset Signaling.
Problem Three: Reset Signaled During Packet.
Transmission.
15. Tree Identification.Tree ID Signaling.
The Tree ID Process.
Leaf Nodes Try to Find Their Parents.
Parents Identify Their Children.
Three Example Scenarios.
Scenario One.
Leaf Nodes Signal Parent_Notify.
Branch Nodes Locate Their Parents.
Scenario Two.
Leaf Nodes Locate Their Parents.
Root Contention.
Scenario Three.
Force Root Delay.
Leaf Nodes Attempt to Locate Their Parents.
Branch Nodes Attempt to Locate Their Parents.
Looped Topology Detection.
16. Self Identification.Self-Identification Signaling.
Physical ID Selection.
Second and Subsequent Physical ID Assignment.
Self-ID Packets.
Self-ID Packet Zero.
Self-ID Packets One and Two (1394a).
Who Uses the Self-ID Packet Information.
IV. SERIAL BUS MANAGEMENT.
17. Cycle Master.Determining and Enabling the Cycle Master.
Cycle Start Packet.
18. Isochronous Resource Manager.Determining the Isochronous Resource Manager.
Minimum Requirements of Isochronous Resource Managers.
Enabling the Cycle Master.
Resource Allocation Registers.
Channel Allocation.
Bus Bandwidth Allocation.
Reallocation of Isochronous Resources.
Power Management.
19. Bus Manager.Determining the Bus Manager.
Power Management.
Power Management by Bus Manager Node.
Power Management by IRM Node.
The Topology Map.
Accessing the Topology Map.
Gap Count Optimization.
The Speed Map.
Accessing the Speed Map.
Bus Bandwidth Set-Aside.
20. Bus Management Services.Serial Bus Control Requests.
Bus Reset Control Request.
Initialize Control Request.
Link-On Control Request.
Present Status.
PHY Configuration Request.
Serial Bus Control Confirmations.
Serial Bus Event Indication.
V. REGISTERS & ROM.
21. CSR Architecture.Core Registers.
Effect of Reset on the CSRs.
State Register (State_Clear & State_Set).
Node_IDS Register.
Reset_Start Register.
Indirect_Address and Indirect_Data Registers.
Split_Timeout Register.
Argument, Test_Start, and Test_Status Registers.
Units_Base, Units_Bound, Memory_Base, and Memory_Bound Registers.
Interrupt_Target and Interrupt_Mask Registers.
Clock_Value, Clock_Tick_Period, Clock_Strobe_Arrived, and Clock_Info Registers.
Message_Request & Message_Response Registers.
Serial Bus Dependent Registers.
Cycle_Time & Bus_Time Registers.
Power_Fail_Imminent & Power_Source Registers.
Busy_Timeout Register.
Bus_Manager_ID Register.
Bandwidth_Available Register.
Channels_Available Register.
Maint_Control Register.
Maint_Utility Register.
Unit Registers.
Topology Map.
Speed Map.
22. PHY Registers.1394-1995 PHY Register Map.
Port Status Registers.
PHY Configuration Packet.
1394a PHY Register Map.
Page Select.
23. Configuration ROM.Minimal ROM Format.
General ROM Format.
Header Information.
Bus_Info_Block (1394-1995).
Bus Info Block (1394a).
Root_Directory.
Company ID Value Administration.
VI. POWER MANAGEMENT.
24. Introduction to Power Management.Review of 1394-1995 Power-Related Issues.
Goals of the 1394a Power Extensions.
25. Cable Power Distribution.Power Distribution.
Power Class Codes.
Power Providers.
Power Consumer.
Self-Powered Nodes (Non Power Providers).
Local Power Down Summary.
26. Suspend & Resume.Suspending a Port.
Suspending Via the Suspend Command Packet.
Suspending Via RX_SUSPEND.
The BIAS Handshake.
Suspending Via Port Disable.
Port Suspend Via Unexpected Loss of Bias.
Resuming Full Operation.
Resuming Via Resume Packet.
Resuming Via Resume Port Command Packet.
Resuming Via Port Events.
27. Power State Management.Power Management.
Power States.
New CSRs.
New ROM Entries.
Appendix: Example 1394 Chip Solutions.Overview.
1394 in the PC.
TSB12LV22 / OHCI-Lynx.
Features.
Overview.
TSB41LV03.
Putting it all Together.
1394 in the Digital Camera.
TSB12LV31 - GPLynx.
TSB21LV03A.
Putting it all Together.
For More Information.
Appendix: Glossary.Index. 0201485354T04062001
Preface
About This Book
The MindShare Architecture Series
The MindShare Architecture book series includes: ISA System Architecture, EISA System Architecture, 80486 System Architecture, PCI System Architecture, Pentium System Architecture, PCMCIA System Architecture, PowerPC System Architecture, Plug-and-Play System Architecture, CardBus System Architecture, Protected Mode Software Architecture, Pentium Pro and Pentium II System Architecture, USB System Architecture, FireWire System Architecture and AGP System Architecture. The book series is published by Addison-Wesley. Rather than duplicating common information in each book, the series uses the building-block approach. ISA System Architecture is the core book upon which the others build.
Cautionary Note
The reader should keep in mind that MindShare's book series often deals with rapidly-evolving technologies. With IEEE 1394, this is particularly true. This book is based in part on several incomplete specifications. This being the case, it should be recognized that the book is a "snapshot" of the state of 1394 technology at the time that the book was completed. We attempt to update each book on a timely basis to reflect changes in the targeted technology, but, due to various factors (waiting for the next version of the specification to be "frozen," the time necessary to make the changes, and the time to produce the books and get them out through the distribution channels), there will always be a delay.
Please check our web site for additions and errata on this and other MindShare books. As specifications and technologies change MindShare maintains errata, clarifications, and additions to the books to ensure that the reader has a way of keeping updated on recent developments (www.mindshare.com).
Organization of This Book
The book is divided into six parts and an appendix. Each part contains the chapters listed below and a brief description of the contents of each chapter.
Part One: Introduction to FireWire (IEEE 1394)
Chapter 1: Why FireWire?
This chapter describes background information regarding the development of the FireWire specification (1394-1995 and the 1394a Supplement) and discusses FireWire applications.
Chapter 2: Overview of the FireWire Architecture
This chapter describes the primary features of the FireWire serial bus implementation. The chapter also reviews the IEEE 1394 standards (IEEE 1394-1995 & IEEE 1394a) and IEEE ISO/IEC 13213 (ANSI/IEEE 1212) standard that the FireWire serial bus is based upon.
Part Two: Serial Bus Communications
Chapter 3: Communication Model
This chapter provides an overview of the serial bus communications model. It defines the basic transfer types and introduces the communication layers defined by the specification.
Chapter 4: Communications Services
This chapter describes the services defined by the specification that are used to pass parameters between layers during the execution of each transaction. The protocol layers and services for asynchronous and isochronous transactions are discussed. Asynchronous transactions exist in three forms: reads, writes, and locks, while isochronous transactions are performed only as writes.
Chapter 5: Cables & Connectors
This chapter discusses the cable characteristics and connectors used by the IEEE 1394 cable environment. It also mentions the Device Bay implementation being specified in PC environments.
Chapter 6: The Electrical Interface
This chapter details the serial bus signaling environment. This includes recognition of device attachment and removal, arbitration signaling, speed signaling, and data/strobe signaling.
Chapter 7: Arbitration
This chapter details the arbitration process. It defines the various types of arbitration including isochronous and asynchronous arbitration, as well as the newer arbitration types defined by the 1394a supplement.
Chapter 8: Asynchronous Packets
Asynchronous transactions exist in three basic forms: reads, writes, and locks. This chapter details the packets that are transmitted over the bus.
Chapter 9: Isochronous Packets
Isochronous transactions are scheduled so that they occur at 125us intervals. This chapter discusses the format of the packet used during isochronous transactions.
Chapter 10: PHY Packet Format
This chapter discusses the various types of PHY packet. The role of each PHY packet is discussed, packet format is specified, and the fields within each packet are detailed.
Chapter 11: Link to PHY Interface
This chapter details the signaling interface between the link and PHY layer controller chips. The 1394a supplement makes this interface mandatory for implementations of separate PHY and link layer chips.
Chapter 12: Transaction Retry
This chapter discusses transaction retries that occur when the recipient of a packet is busy (e.g. has a buffer full condition). Two retry mechanisms are defined by the 1394 specification: single and dual phase. Each type of mechanism is discussed. Software may also initiate retries for transactions that fail.
Part Three: Serial Bus Configuration
Chapter 13: Configuration Process
This chapter overviews the configuration process comprising the initialization, tree ID, and self-ID phases. Once self-ID completes, additional configuration may optionally take place in the form of bus management activities that are also reviewed in this chapter.
Chapter 14: Bus Reset (Initialization)
This chapter details the bus reset phase of the cable configuration process. Initialization begins with the assertion of a bus reset by a given node on the bus. This chapter discusses the reset enhancements introduced by the 1394a supplement; debouncing the bias change detection, arbitration (short) bus reset, and new timing parameters.
Chapter 15: Tree Identification
Following bus initialization, the tree ID process begins to determine which node will become the root. This chapter details the protocol used in determining the topology of the serial bus.
Chapter 16: Self Identification
This chapter focuses on the self-ID process. During self-ID all nodes are assigned addresses and specify their capabilities by broadcasting self-ID packets.
Part Four: Serial Bus Management
Chapter 17: Cycle Master
This chapter describes the role of the cycle master node, and defines how the cycle master is identified and enabled.
Chapter 18: Isochronous Resource Manager
This chapter describes the role of the isochronous resource manager: how it is identified and enabled, and how other nodes interact with it.
Chapter 19: Bus Manager
In this chapter, the bus manager function is described including topology map and speed map generation and access, as well as power management.
Chapter 20: Bus Management Services
This chapter discusses the bus management services used by the bus manager and isochronous resource manager to perform their bus management roles.
Part Five: Registers and Configuration ROM
Chapter 21: CSR Architecture
This chapter discusses the CSR registers defined by the ISO 13213 specification with particular focus on the registers that are required by the 1394 specification.
Chapter 22: PHY Registers
This chapter introduces the PHY register map and port registers. Both the 1394-1995 and the 1394a PHY registers are detailed.
Chapter 23: Configuration ROM
This chapter details the contents of configuration ROM required by the ISO/IEC 13213 specification. The serial bus also defines ROM entries that are required by some nodes, depending on the capabilities.
Part Six: Power Management
Chapter 24: Introduction to Power Management
This chapter provides a brief introduction to the power management environment introduced by the 1394a specification. The chapter introduces the three documents that further define the power management specification: Cable Power Distribution, Suspend/Resume Mechanisms, and Power State Management.
Chapter 25: Cable Power Distribution
This chapter discusses power distribution in the cable environment. It discusses the four power types designations for nodes: power providers, alternate power providers, power consumers, and self-powered devices. Details regarding the power implementation of nodes in also included.
Chapter 26: Suspend & Resume
This chapter introduces the suspend and resume mechanisms. This capability allows the PHY layer within a node to enter a low power state under software control (either local node software or from another node). The mechanisms implemented for suspend and resume are detailed including: command and confirmation packets, suspend initiator actions, suspend target actions, and related suspend and resume signaling. The impact on PHY and port register definition is also discussed.
Chapter 27: Power State Management
This chapter describes the CSR registers and ROM entries that define power management capabilities and provide the mechanisms for controlling the power states of a node and of local units within a node.
Appendix
Example 1394 Chip Solutions
This chapter is provided by Texas Instruments and discusses a variety of 1394 component implementations.
Target Audience
This book is intended for use by hardware and software design and support personnel. Due to the clear, concise explanatory methods used to describe each subject, personnel outside of the design field may also find the text useful. This book is perhaps best used prior to reading the IEEE 1394-1995 specification and 1394a Supplement. It provides the important context, concepts, and relationships that are essential for understanding the specifications.
Prerequisite Knowledge
The reader should be familiar with computer architectures.
Documentation Conventions
This document contains conventions that are used in other MindShare books and in the IEEE 1394 documentation. Since this book is a companion to the specification, many of the standard documentation conventions are used here to ease the transition between the two documents.
Labels for Multi-byte Blocks
The CSR Architecture and the IEEE 1394 standards attempt to eliminate confusion of terminology relating to the terms: word as it applies to the size of an aligned block of bytes in address space. Depending on the manufacturer, a "word" may refer to 2 bytes or to 4 bytes. The IEEE standards chooses to define multibytes as follows:
nibble (4-bits)
byte (8-bits)
doublet (two bytes)
quadlet (four bytes)
octlet (eight bytes)
Hexadecimal Notation
This section defines the typographical convention used throughout this book. Hex Notation All hex numbers are followed by an "h." Examples:
9A4Eh
0100h
Binary Notation
All binary numbers are followed by a "b." Examples:
0001 0101b
01b
Decimal Notation
Numbers without any suffix are decimal. When required for clarity, decimal numbers are followed by a "d." The following examples each represent a decimal number:
16
255
256d
128d
Bits versus Byte Notation
This book employs the standard notation for differentiating bits versus bytes. All abbreviations for "bits" use lower case. For example:
1.5Mb/s
2Mb
All references to "bytes" are specified in upper case. For example:
10MB/s
1KB
Identification of Bit Fields (logical groups of bits or signals)
All bit fields are designated in little-endian bit ordering:
X::Y,
where "X" is the most-significant bit and "Y" is the least-significant bit of the field.
Visit Our Web Site
Our web site contains a listing of all of our courses and books. In addition, it contains errata for a number of the books, a hot link to our publisher's web site, and course outlines: http://www.mindshare.com.
We Want Your Feedback
MindShare values your comments and suggestions. You can contact us via mail, phone, fax, or internet e-mail.
Phone: (972) 231-2216, and, in the U.S., (800) 633-1440
Fax: (972) 783-4715
E-mail: mindshar@interserv.com
E-mail: don@mindshare.com
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Mailing Address:
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0201485354P04062001
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