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Computer Organization and Architecture: Designing for Performance, 8th Edition

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Computer Organization and Architecture: Designing for Performance, 8th Edition

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Features

Multiple Perspectives: Systems are viewed from both the architectural (attributes of a system visible to a machine language programmer) and organizational (operational units and their interconnections that realize the architecture) perspectives to give students context.

Unified Treatment of I/O: Provides full understanding of I/O functions and structures, including two important external interface examples: FireWire and InfiniBand.

Focus on RISC: Students gain a broad understanding of this technology, found in virtually all contemporary machines.

Parallel Processors: Exceptionally clear, well-organized treatment of symmetric multiprocessors (SMP), clusters, and NUMA systems.

Running Case Studies: Case studies of Intel x86 and embedded ARM architectures supplement and explain material.

Microprogrammed Implementation: This technology is given a full treatment, so students gain a complete understanding of processor organization.

Description

  • Copyright 2010
  • Edition: 8th
  • Premium Website
  • ISBN-10: 0-13-607373-5
  • ISBN-13: 978-0-13-607373-4

Four-time winner of the best Computer Science and Engineering textbook of the year award from the Textbook and Academic Authors Association, Computer Organization and Architecture: Designing for Performance provides a thorough discussion of the fundamentals of computer organization and architecture, covering not just processor design, but memory, I/O, and parallel systems. Coverage is supported by a wealth of concrete examples emphasizing modern RISC, CISC, and superscalar systems. Undergraduates and professionals in computer science, computer engineering, and electrical engineering courses will learn the fundamentals of processor and computer design from this award-winning text.

The eighth revision has been updated to reflect major advances in computer technology, including multicore processors and embedded processors. Interactive simulations have been expanded and keyed into relevant sections of text.

Sample Content

Table of Contents

Chapter 0 Reader's Guide

0.1 Outline of the Book

0.2 A Roadmap For Readers and Instructors

0.3 Why Study Computer Organization and Architecture

0.4 Internet and Web ResourcesPART ONE OVERVIEW

Chapter 1 Introduction

1.1 Organization and Architecture

1.2 Structure and Function

1.3 Key Terms and Review QuestionsChapter 2 Computer Evolution and Performance

2.1 A Brief History of Computers

2.2 Designing for Performance

2.3 The Evolution of the Intel x86 Architecture

2.4 Embedded Systems and the ARM

2.5 Performance Assessment

2.6 Recommended Reading and Web Sites

2.7 Key Terms, Review Questions, and ProblemsPART TWO THE COMPUTER SYSTEM

Chapter 3 A Top-Level View of Computer Function and Interconnection

3.1 Computer Components

3.2 Computer Function

3.3 Interconnection Structures

3.4 Bus Interconnection

3.5 PCI

3.6 Recommended Reading and Web Sites

3.7 Key Terms, Review Questions, and Problems

3A Timing Diagrams

Chapter 4 Cache Memory

4.1 Computer Memory System Overview

4.2 Cache Memory Principles

4.3 Elements of Cache Design

4.4 Pentium 4 Cache Organization

4.5 ARM Cache Organization

4.6 Recommended Reading

4.7 Key Terms, Review Questions, and Problems

Appendix 4A Performance Characteristics of Two-Level Memorie

Chapter 5 Internal Memory Technology

5.1 Semiconductor Main Memory

5.2 Error Correction

5.3 Advanced DRAM Organization

5.4 Recommended Reading and Web Sites

5.5 Key Terms, Review Questions, and ProblemsChapter

6 External Memory

6.1 Magnetic Disk

6.2 RAID

6.3 Optical Memory

6.4 Magnetic Tape

6.5 Recommended Reading and Web Sites

6.6 Key Terms, Review Questions, and ProblemsChapter

 7 Input/Output

7.1 External Devices

7.2 I/O Modules

7.3 Programmed I/O

7.4 Interrupt-Driven I/O

7.5 Direct Memory Access

7.6 I/O Channels and Processors

7.7 The External Interface: FireWire and Infiniband

7.8 Recommended Reading and Web Sites

7.9 Key Terms, Review Questions, and Problems

Chapter 8 Operating System Support

8.1 Operating System Overview

8.2 Scheduling

8.3 Memory Management

8.4 Pentium Memory Management

8.5 ARM Memory Management

8.6 Recommended Reading and Web Sites

8.7 Key Terms, Review Questions, and Problems

Chapter 9 Computer Arithmetic

9.1 The Arithmetic and Logic Unit (ALU)

9.2 Integer Representation

9.3 Integer Arithmetic

9.4 Floating-Point Representation

9.5 Floating-Point Arithmetic

9.6 Recommended Reading and Web Sites

9.7 Key Terms, Review Questions, and Problems

Chapter 10 Instruction Sets: Characteristics and Functions

10.1 Machine Instruction Characteristics

10.2 Types of Operands

10.3 Intel x86 and ARM Data Types

10.4 Types of Operations

10.5 Intel x86 and ARM Operation Types

10.6 Recommended Reading

10.7 Key Terms, Review Questions, and Problems

Chapter 11 Instruction Sets: Addressing Modes and Formats

11.1 Addressing

11.2 x86 and ARM Addressing Modes

11.3 Instruction Formats

11.4 x86 and ARM Instruction Formats

11.5 Assembly Language

11.6 Recommended Reading

11.7 Key Terms, Review Questions, and Problems

Chapter 12 Processor Structure and Function

12.1 Processor Organization

12.2 Register Organization

12.3 The Instruction Cycle

12.4 Instruction Pipelining

12.5 The x86 Processor Family

12.6 The ARM Processor

12.7 Recommended Reading

12.8 Key Terms, Review Questions, and Problems

Chapter 13 Reduced Instruction Set Computers (RISCs)

13.1 Instruction Execution Characteristics

13.2 The Use of a Large Register File

13.3 Compiler-Based Register Optimization

13.4 Reduced Instruction Set Architecture

13.5 RISC Pipelining

13.6 MIPS R4000

13.7 SPARC

13.8 The RISC versus CISC Controversy

13.9 Recommended Reading

13.10 Key Terms, Review Questions, and Problems

Chapter 14 Instruction-Level Parallelism and Superscalar Processors

14.1 Overview

14.2 Design Issues

14.3 Pentium 4

14.4 ARM Cortex-A8

14.5 Recommended Reading

14.6 Key Terms, Review Questions, and ProblemsPART FOUR THE CONTROL UNIT

Chapter 15 Control Unit Operation

15.1 Micro-operations

15.2 Control of the Processor

15.3 Hardwired Implementation

15.4 Recommended Reading

15.5 Key Terms, Review Questions, and ProblemsChapter 16 Microprogrammed Control

16.1 Basic Concepts

16.2 Microinstruction Sequencing

16.3 Microinstruction Execution

16.4 TI 8800

16.5 Recommended Reading

16.6 Key Terms, Review Questions, and ProblemsPART FIVE PARALLEL ORGANIZATION

Chapter 17 Parallel Processing1

7.1 The Use of Multiple Processors

17.2 Symmetric Multiprocessors

17.3 Cache Coherence and the MESI Protocol

17.4 Multithreading and Chip Multiprocessors

17.5 Clusters

17.6 Nonuniform Memory Access Computers

17.7 Vector Computation

17.8 Recommended Reading and Web Sites

17.9 Key Terms, Review Questions, and Problems

Chapter 18 Multicore Computers

18.1 HardwarePerformance Issues

18.2 Software Performance Issues

18.3 Multicore Organization

18.4 Intel x86 Multicore Organization

18.5 ARM11 MPCore

18.6 Recommended Reading and Web Sites

18.7 Key Terms, Review Questions, and ProblemsAPPENDIX A Projects for Teaching Computer Organization and

Architecture

A.1 Interactive Simulations

A.2 Research Projects

A.3 Simulation Projects

A.4 Reading/Report Assignments

A.5 Writing Assignments

A.6 Test BankAppendix

B Assembly Language, Assemblers, and Compilers

B.1 Assembly Language

B.2 Assemblers

B.3 Loading and Linking

B.4 Recommended Reading and Web Site

B.5 Key Terms, Review Questions, and ProblemsONLINE CHAPTERS

WilliamStallings.com/COA/COA8e.htm

lChapter 19 Number Systems

19.1 The Decimal System

19.2 The Binary System

19.3 Converting between Binary and Decimal

19.4 Hexadecimal Notation

19.5 Key Terms, Review Questions, and Problems

Chapter 20 Digital Logic

20.1 Boolean Algebra

20.2 Gates

20.3 Combinational Circuits

20.4 Sequential Circuits

20.5 Programmable Logic Devices

20.6 Recommended Reading and Web Site

20.7 Key Terms and Problems

Chapter 21 The IA-64 Architecture

21.1 Motivation

21.2 General Organization

21.3 Predication and Speculation

21.4 IA-64 Instruction Set Architecture

21.5 Itanium Organization

21.6 Recommended Reading and Web Sites

21.7 Key Terms, Review Questions, and ProblemsONLINE APPENDICES

WilliamStallings.com/COA/COA8e.htmlAppendix C Hash Tables

Appendix D Victim Cache

Appendix E Interleaved Memory

Appendix F International Reference Alphabet

Appendix G Virtual Memory Page Replacement Algorithms

Appendix H Recursive Procedures

Appendix I Additional Instruction Pipeline TopicsH.1 Pipeline Reservation Tables

H.2 Reorder Buffers

H.3 Scoreboarding

H.4 Tomasulo's AlgorithmReferences

Glossary

Index

Acronyms

Updates

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