Mike Peng Li
Dr. Mike Peng Li was the Chief Technology Officer (CTO) with Wavecrest. He is now a Principle Architecture/Distinguished Engineer with Altera. Dr. Li pioneered the jitter separation method (Tailfit); deterministic jitter (DJ), random jitter (RJ), and total jitter (TJ) concept and theory formation; and the jitter transfer function (JTF) concept, theory, and application for high-speed serial link analysis. He has set and contributed to standards for jitter, noise, and signal integrity for leading serial data communications, such as Fibre Channel, Gigabit Ethernet, Serial ATA, PCI Express, FB DIMM, and International Technology Roadmap for Semiconductors (ITRS). He has been the cochairman of the PCI Express jitter standard committee. Dr. Li has been involved in technical committees for IEEE- and IEC-sponsored technical conferences, such as International Test Conference (ITC) and DesignCon. He is a frequent speaker, invited author/speaker, panelist, and session and panel chair on the subjects of jitter/noise and signal integrity, covering both design and testing. He has received many awards, including a design paper award from DesignCon/IEC and a contribution award from PCI-SIG. He has been listed in Who’s Who in America and Who’s Who in the World since 2006.
Dr. Li has more than 15 years of experience in high-speed-related measurement instrumentation, testing, and analysis/modeling algorithms and tools, with applications in IC, microprocessor, clock, serial data communications for electrical and optical, and wireless communication. He has a BS in physics from the University of Science and Technology in China and an MSE in electrical engineering and a PhD in physics from the University of Alabama in Huntsville. He did his post-doctorate work at the University of California, Berkeley, where he worked as a research scientist on high-energy astrophysics before he joined industry. Dr Li has published more than 80 papers in refereed technical journals and conferences. He has filed 12 patents, with four granted and eight pending. He was the executive editor for Design and Test for Multiple Gbps Communication Devices and Systems and wrote two contributing chapters on jitter, signal integrity, and high-speed I/O design and testing for two books.