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1.3 Pre-emphasis

Pre-emphasis is a way to boost only the signal's high-frequency components, while leaving the low-frequency components in their original state. Pre-emphasis operates by boosting the high-frequency energy every time a transition in the data occurs. The data edges contain the signal's high-frequency content. The signal edges deteriorate with the loss of the high-frequency signal components. A simple pre-emphasis circuit can be constructed from a two-tap finite impulse response (FIR) filter. The circuitry works by comparing the previously transmitted data bit to the current data bit, where the circuit block Z–1 provides the delay for a single data bit. If the two bits—the delayed bit and the current bit—are the same level, the current bit is transmitted at the normal level. If the two bits are different, the current bit is transmitted at a higher magnitude. Figure 1-4 shows the FIR filter block diagram and associated waveforms.

Figure 1-4

Figure 1-4 Block schematic of a FIR filter pre-emphasis circuit where the percentage of pre-emphasis is programmable.

The pre-emphasis circuit is primarily designed to overcome frequency-dependent attenuation.

1.3.1 Pre-emphasis Measurement

There are many different methods of measuring pre-emphasis. Although it is not important to follow a particular measurement method, it is important for the engineer to understand a particular definition when modeling his or her system. For example, Figure 1-5 shows the pre-emphasis measurement method used in an Altera programmable logic device. The waveform is part of a differential signal.

Figure 1-5

Figure 1-5 Waveform definition of pre-emphasis.

The pre-emphasis circuitry within a modern programmable device such as the Altera Stratix has an architecture that can be dynamically programmed to five different levels of pre-emphasis. The exact value of pre-emphasis cannot be predetermined, because each device requires a percentage of pre-emphasis that is dependent on the output signal strength and transmission path characteristics. Table 1-2 shows five possible programmable pre-emphasis levels for a differential drive signal (VOD) of 800 mV. In this case the internal termination is 100 ohms. The amount of pre-emphasis changes according to the transmission path parameters.

Table 1-2. Typical Percentage Pre-emphasis Levels for a Programmable Logic Device with an 800 mV Drive Signal (VOD)

Programmable Setting

Typical Pre-emphasis Level

1

11%

2

36%

3

65%

4

100%

5

140%

1.3.2 Receiver Equalization

An alternative to pre-emphasis is receiver equalization, which provides functionality in the receiver to help overcome the high-frequency signal losses of the transmission medium. Receiver equalization acts as a high-pass filter and amplifier to the data as it enters the receiver. In effect, equalization distorts the received data, correcting the distortion of the signal resulting from the high-frequency losses. This allows the receiver to rebuild the signal and interpret it successfully. External receiver equalization can be implemented with external filter networks. However, these filters require extra components with added PCB tracks and PCB stubs that require careful design if signal integrity problems are to be avoided. Furthermore, a fixed filter circuit is difficult to adapt for differing loss.

Some modern digital devices include equalization within the receiver. In a number of programmable logic devices, the equalization function is dynamically controllable. The equalization setting typically depends on the application and environment. For example, the receiver equalization would be up to 9 dB of gain for a 40-inch FR4 backplane. Moreover, data dispersion can be overcome when an equalizer is designed to cut off unwanted frequency components that spread symbols. The equalizer brings the symbols back into shape and time, thereby minimizing or eliminating PJD.

1.3.3 Maintaining Signal Integrity in Legacy Systems

The expansion of high-speed interfaces has led to some dilemmas because designers generally need to use legacy systems to support existing components or interfaces and reduce the cost of replacing an entire infrastructure. For example, this means that backplanes designed to operate at 1 Gbps are now required to run at 2.5 Gbps and faster to support existing and new components. In some circumstances this may be possible with the combined use of pre-emphasis and equalization. Equalization can compensate for many of the issues of the legacy backplane, such as narrow PCB tracking, which typically suffers from increased signal attenuation as transmission frequencies increase. However, equalization is relatively new as an integral part of logic receivers, so it is possible that legacy cards plugged into a system will not include equalization. This means that higher levels of pre-emphasis are required to ensure reliable communications. It is not uncommon for pre-emphasis levels in excess of 100% to be used in legacy applications. Normally each system and application require a unique setting for pre-emphasis, equalization, and drive strength. It is therefore important to model the entire data communication path using accurate model descriptions for the PCB interconnect and transceiver interfaces to ensure that the entire system is matched from within the driver to the internal receiver circuitry. In conclusion, it is clear that skin effect and dielectric loss can cause significant attenuation to the high-frequency content of signals. For example, this can impact the success of communicating high-speed data via a conventional FR4 PCB. The use of pre-emphasis and equalization can help the signal integrity of a transmission path, provided that you carefully select the parameters.

1.3.4 Simultaneous Switching Outputs

Although high-speed data rates correlate with high-frequency signals, it is the signal edge timing that has the most detrimental effect on signal integrity. This is particularly true as systems migrate to dense, highly integrated, high-speed switching systems where typically hundreds of pins are switching with edge rise and fall times that generally are faster than 500 picoseconds. A consequence of a large number of quickly switching device connections is the unstable power supply voltage, where greater power demanded in short time periods causes transient disturbances. Traditionally designers have decoupled power supplies to minimize transient charges and stabilize power sources. Nevertheless, new high-speed, high-density systems require very careful design to minimize power supply transients, or the result is a phenomenon called simultaneous switching noise (SSN).

Moreover, as digital circuitry increases in speed and output switching times decrease, higher transient currents occur within the device output circuits as the effective output load capacitors discharge. This sudden flow of current exits the device through internal inductances to a PCB ground plane. This causes a transient voltage to develop, which is a voltage difference between the device output and the board ground. This is known colloquially as ground bounce, but in actuality an unwanted signal return current causes transient variations in the ground voltage. The signal return currents or bounce effect can cause an output low ground signal to be seen as a high-output signal by other devices in the system. You can reduce unwanted signal return currents by following a number of classic design rules. Nonetheless, a number of programmable device manufacturers now provide pin slew rate control, which allows the designer to slow an edge rate and therefore reduce ground current transients or ground bounce effects. Additionally, most modern devices include multiple power and ground pins. This allows the designer to locate a high-speed input or output pin close to a ground pin to reduce the effects of simultaneous switching outputs (SSOs).

The challenges of high-speed design require some additional effort to ensure signal integrity. This can be achieved by following some simple analog design rules and by using careful PCB layout techniques. Nonetheless, contemporary integrated circuit manufacturers are providing many features to compensate for PCB anomalies and support high-speed design. Programmable slew rate control and programmable on-chip termination technology are helping make the designers' work somewhat easier. However, programmable pre-emphasis, equilisation, and slow rate control only work in stable systems, and they are not a substitute for good design practice.

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