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The FPGA as a Computing Platform

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This chapter presents a brief overview of FPGAs and FPGA-based platforms and present the general philosophy behind using the C language for FPGA application development. Even experienced FPGA users will find new information as the FPGA is applied to new, perhaps unfamiliar territory: that of high-performance computing.
This chapter is from the book

This chapter is from the book

As the cost per gate of FPGAs declines, embedded and high-performance systems designers are being presented with new opportunities for creating accelerated software applications using FPGA-based programmable hardware platforms. From a hardware perspective, these new platforms effectively bridge the gap between software programmable systems based on traditional microprocessors, and application-specific platforms based on custom hardware functions. From a software perspective, advances in design tools and methodology for FPGA-based platforms enable the rapid creation ofhardware-accelerated algorithms.

The opportunities presented by these programmable hardware platforms include creation of custom hardware functions by software engineers, later design freeze dates, simplified field updates, and the reduction or elimination of custom chips from many categories of electronic products. Increasingly, systems designers are seeing the benefits of using FPGAs as the basis for applications that are traditionally in the domain of application-specific integrated circuits (ASICs). As FPGAs have grown in logic capacity, their ability to host high-performance software algorithms and complete applications has grown correspondingly.

In this chapter, we will present a brief overview of FPGAs and FPGA-based platforms and present the general philosophy behind using the C language for FPGA application development. Experienced FPGA users will find much of this information familiar, but nonetheless we hope you stay with us as we take the FPGA into new, perhaps unfamiliar territory: that of high-performance computing.

1.1 A Quick Introduction to FPGAs

A field-programmable gate array (FPGA) is a large-scale integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. The term "field-programmable" refers to the ability to change the operation of the device "in the field," while "gate array" is a somewhat dated reference to the basic internal architecture that makes this after-the-fact reprogramming possible.

FPGAs come in a wide variety of sizes and with many different combinations of internal and external features. What they have in common is that they are composed of relatively small blocks of programmable logic. These blocks, each of which typically contains a few registers and a few dozen low-level, configurable logic elements, are arranged in a grid and tied together using programmable interconnections. In a typical FPGA, the logic blocks that make up the bulk of the device are based on lookup tables (of perhaps four or five binary inputs) combined with one or two single-bit registers and additional logic elements such as clock enables and multiplexers. These basic structures may be replicated many thousands of times to create a large programmable hardware fabric.

In more complex FPGAs these general-purpose logic blocks are combined with higher-level arithmetic and control structures, such as multipliers and counters, in support of common types of applications such as signal processing. In addition, specialized logic blocks are found at the periphery of the devices that provide programmable input and output capabilities.

Common FPGA Characteristics

FPGAs are mainly characterized by their logic size (measured either by the number of transistors or, more commonly, by the number of fundamental logic blocks that they contain), by their logic structure and processing features, and by their speed and power consumption. While they range in size from a few thousand to many millions of logic gate equivalents, all FPGAs share the same basic characteristics:

  • Logic elements. All FPGA devices are based on arrays of relatively small digital logic elements. To use such a device, digital logic problems must be decomposed into an arrangement of smaller logic circuits that can be mapped to one or more of these logic elements, or logic cells, through a process of technology mapping. This technology mapping process may be either manual or automatic, but it involves substantial intelligence on the part of the human or (more typically) the software program performing the mapping.

  • Lookup tables. FPGA logic elements are themselves usually composed of at least one programmable register (a flip-flop) and some input-forming logic, which is often implemented as a lookup table of n inputs, where n is generally five or less. The detailed structure of this logic element depends on the FPGA vendor (for example, Xilinx or Altera) and FPGA family (for example, Xilinx Virtex or Altera Cyclone). The lookup tables (LUTs) that make up most logic elements are very much akin to read-only memory (ROM). These LUTs are capable of implementing any combinational function of their inputs.

  • Memory resources. Most modern FPGA devices incorporate some on-chip memory resources, such as SRAM. These memories may be accessible in a hierarchy, such as local memory within each logic element combined with globally shared memory blocks.

  • Routing resources. Routing is the key to an FPGA’s flexibility, but it also represents a compromise—made by the FPGA provider—between programming flexibility and area efficiency. Routing typically includes a hierarchy of channels that may range from high-speed, cross-chip long lines to more flexible block-to-block local connections. Programmable switches (which may be SRAM-based, electrically erasable, or one-time-programmable) connect the on-chip FPGA resources to each other, and to external resources as well.

  • Configurable I/O. FPGA-based applications have a wide variety ofsystem-level interface requirements and therefore FPGAs have many programmable I/O features. FPGA pins can be configured as TTL, CMOS, PCI, and more, allowing FPGAs to be interfaced with, and convert between, many different circuit technologies. Most FPGAs also have dedicated high-speed I/Os for clocks and global resets, and many FPGAs include PLLs and clock management schemes, allowing designs with multiple independent clock domains to be created and managed.

FPGA Programming Technologies

FPGA programming technologies range from one-time-programmable elements (such as those found in devices from Actel and Quicklogic) to electrically erasable or SRAM-based devices such as those available from Altera, Lattice Semiconductor, and Xilinx.

While most FPGAs in use today are programmed during system manufacturing to perform one specific task, it is becoming increasingly common for FPGAs to be reprogrammed while the product is in the field. For SRAM-based and electrically erasable FPGAs this field upgrading may be as simple as providing an updated Flash memory card or obtaining a new binary device image from a website or CD-ROM.

Hardware applications implemented in FPGAs are generally slower and consume more power than the same applications implemented in custom ASICs. Nonetheless, the dramatically lowered risk and cost of development for FPGAs have made them excellent alternatives to custom ICs. The reduced development times associated with FPGAs often make them compelling platforms for ASIC prototyping as well.

Many modern FPGAs have the ability to be reprogrammed in-system, in whole or in part. This has led some researchers to create dynamically reconfigurable computing applications within one or more FPGAs in order to create extremely high-performance computing systems. The technology of reconfigurable computing is still in its infancy, however, due in large part to the high cost, in terms of power and configuration time, of dynamically reprogramming an FPGA. We will examine some of this research and make predictions regarding the future of reconfigurable computing in a later chapter.

Defining the behavior of an FPGA (the hardware that it contains) has traditionally been done either using a hardware description language (HDL) such as VHDL or Verilog or by arranging blocks of pre-existing functions, whether gate-level logic elements or higher-level macros, using a schematic- or block diagram-oriented design tool. More recently, design tools such as those described in this book that support variants of the C, C++, and Java languages have appeared. In any event, the result of the design entry process (and of design compilation and synthesis, as appropriate) is an intermediate file, called a netlist, that can be mapped to the actual FPGA architecture using proprietary FPGA place-and-route tools. After placement and mapping the resulting binary file—the bitmap—is downloaded to the FPGA, making it ready for use.

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