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Introduction to Power Integrity for I/O Interfaces

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It is becoming increasingly essential to determine not only the PDN noise, but also the margin degradation due to the noise coupling to signals. System designers need to consider a concurrent design methodology to evaluate power integrity and its effects on signal integrity.
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In a digital electronic system, when high-speed signals pass through the interconnect network, different unwanted effects such as Inter Symbol Interference (ISI) and crosstalk are produced that degrade the signal integrity. Power integrity is related to noise in the Power Distribution Network (PDN). Various techniques have been developed to model and design the PDN and analyze the noise impact [1, 2]. Simultaneously Switching Output (SSO) noise is produced when charging/discharging currents from the multiple buffers go through the PDN. This noise affects the circuit response and produces timing skews and delays. The power noise is coupled to signals at the chip level and at the interconnect level. It is becoming increasingly essential to determine not only the PDN noise, but also the margin degradation due to the noise coupling to signals. Due to ISI, crosstalk, SSO, and combinations thereof, the signal quality and timing margin becomes degraded at the receiver. System designers need to consider a concurrent design methodology to evaluate power integrity and its effects on signal integrity.

1.1 Digital Electronic System

The digital electronic system comprises a processing unit and an I/O controller unit. Different types of data flow from one part of the system to others in digital format, on different buses. Internal buses communicate within the different components of the system, and external buses communicate with the external devices. Various networking devices communicate with the digital electronic system with different protocols and standards. The I/O controller unit manages various types of input and output data on the buses and networking devices. The processing unit and the I/O controller unit are on different integrated circuits or chips in a conventional personal computer system, whereas they are on the same chip in a System-on-chip– (SoC) based platform. The I/O controller unit has several I/O interfaces that communicate with different I/Os. Figure 1.1 shows the block diagram of a typical I/O interface in a digital system.

Figure 1.1

Figure 1.1 Input output interface

A typical I/O interface has a logic block, clocking scheme, transmitter block, and receiver block. The logic block consists of digital circuits that communicate with the processing unit. The clocking is based on individual interface architecture and provides clocking for transmitter and receiver blocks. It can include Phase Locked Loops (PLLs) or Delay Lock Loops (DLLs). There are two types of I/O interfaces: a single-ended interface and a differential interface. The transmitter unit has high-speed digital circuits and a final stage driver unit. Transmitter high-speed digital circuits can include a predriver, equalizer, multiplexer, and parallel-to-serial converter, and so on, depending on the architecture and interface type. Similarly, the receiver block has high-speed digital circuits and a final stage receiver unit. Receiver high-speed digital circuits can include a sampling amplifier, serial-to-parallel converter, and so on, depending on the interface type and architecture. Single-ended and differential interfaces have different types of drivers, receivers, and high-speed digital circuits.

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