SOC Design Verification
In Chapter 1, we introduced the concept of SOCs and IPs. We also discussed some of the SOC design challenges. In this chapter, we complete our discussion of SOCs. We will cover physical design issues related to SOCs in Chapter 4.
Section 3.2 covers design for integration. Here we cover more about on-chip buses (OCBs) and continue with the example we used in Chapter 1 on VoIP.
Section 3.3 discusses SOC verification. The verification methods that we covered in Chapter 2 for ASIC design verification can also be used for SOCs. However, we will discuss additional issues affecting SOCs, in particular those that are due to the usage of several IPs on an SOC. The earlier these issues are addressed in the SOC design cycle, the faster and more complete will be the verification process.
We end this chapter with a complete example for an SOC. Section 3.4 covers a set-top box (STB) design example. The example shows architectural investigation and modeling to show the efficacy of a specific on-chip communication network as a unifying communications medium and it shows a new, unified memory architecture with end-to-end performance guarantees.